What's the ''OTG_DEACHINT'' register in the STM32F7's USB core used for?

Posted on November 28, 2016 at 19:12

The documentation of the Synopsis-supplied USB IPs in the STM32 RMs is... ehm... hard to find a politically correct expression for it. It's true that the documentation is just a modified version of what ST received from Synopsis, but it's still ST's responsibility towards its clients to get it into proper shape, IMO. I've started a [DEAD LINK /public/STe2ecommunities/mcu/Lists/cortex_mx_stm32/Flat.aspx?RootFolder=/public/STe2ecommunities/mcu/Lists/cortex_mx_stm32/%27L4%20Cube%20-%20clearing%20OTG_GINTSTS%20bits&FolderCTID=0x01200200770978C69A1141439FE559EB459D7580009C4E14902C3CDE46A77F0FFD06506F5B]thread recently as I had a couple of similar questions towards USB, having received only a snippet of answer, and I am disappointed enough not to ask more questions in this regard even if there are many.

You can find partial answers in manuals for other chips employing the Synopsis USB IP (even if some of them are even worse than ST's). For DEACHINT, I've found this:

Bits in this register are set and cleared when the application sets and clears bits in the corresponding Device Endpoint-n Interrupt register (DIEPINTn/DOEPINTn).

 

As I understand it then, bit n/16+n is OR of all the bits in respective DIEPINTn/DOEPINTn (so bits in this register are logically read-only).

> Why is it only for endpoint 1?

Good question. My personal bet is, that it's been a tradeoff between silicon array and benefit of having a single interrupt signal for the most used endpoint.

JW

Posted on November 29, 2016 at 17:15

I can't tell you how happy I am that there is someone else suffering with me!  We can hang out on this thread and try to figure this mess out together, because the DEACHINT register is definitely not the only thing I'm struggling with.

>The documentation of the Synopsis-supplied USB IPs in the STM32 RMs is... ehm... hard to find a politically correct expression for it.

Yes!  Thank you!  I've implemented USB firmware on 2 other MCUs (both Atmel), and it was much easier than this train wreck.  Too bad, because the microcontroller seems pretty good aside from this.

>You can find partial answers in manuals for other chips employing the Synopsis USB IP 

What other micros use this IP?  The only way we know that the STM32F746 uses synopsis IP is because the datasheet says ''Portions copyright... Synopsis, Inc.'' at the top of chapter 37.  I'm not really sure of an easy way to search for other micros that use this.

>

As I understand it then, bit n/16+n is OR of all the bits in respective DIEPINTn/DOEPINTn (so bits in this register are logically read-only).

That's what I thought at first, but it looks like the OTG_DAINT register already does that.

Are you still actively developing a USB peripheral?

Posted on November 29, 2016 at 18:21

>>You can find partial answers in manuals for other chips employing the Synopsis USB IP 

>What other micros use this IP? 

Look at that thread I gave link, Tsuneo pointed out that the SiLabs/ex-EnergyMicro Geckos use them.  I then googled for register names, but found only a few, indeed.

>>

As I understand it then, bit n/16+n is OR of all the bits in respective DIEPINTn/DOEPINTn (so bits in this register are logically read-only).

>That's what I thought at first, but it looks like the OTG_DAINT register already does that.

It's sort of parallel; apparently intended to be merged in a multi-USB (or other similar core) setup to a common interrupt. Find ''CME M7 Family FPGA User Guide'', Fig.18-14 ''Interrupt Hierarchy'' at page 399 (apparently a non-vector drawing, IMO taken as a bitmap from Synopsis' documentation).

> Are you still actively developing a USB peripheral?

On hold curerntly, but will need to return to it within a couple of days (sigh).

JW

Posted on November 29, 2016 at 21:33

>>>You can find partial answers in manuals for other chips employing the Synopsis USB IP 

>>What other micros use this IP?  

>Look at that thread I gave link, Tsuneo pointed out that the SiLabs/ex-EnergyMicro

Geckos use them.  I then googled for register names, but found only a few, indeed.

Found it!  Thank you.  Hopefully the gecko docs will help.

Do you know if there are any docs from synopsis?  Synopsis have a few things on its website, but you need to have some sort of confidential access to their data.  The university I work for might have access... I will have to check.

In the mean time, are you aware of any public Synopsis docs?

>>>As I understand it then, bit n/16+n is OR of all the bits in respective DIEPINTn/DOEPINTn (so bits in this register are logically read-only).

>>That's what I thought at first, but it looks like the OTG_DAINT register already does that.

>It's sort of parallel; apparently intended to be merged in a multi-USB (or other similar core) setup to a common interrupt. Find ''CME M7 Family FPGA User Guide'', Fig.18-14 ''Interrupt Hierarchy'' at page 399 (apparently a non-vector drawing, IMO taken as a bitmap from Synopsis' documentation).

A similar figure appears in the STM32F74xxxx docs on page 1322.

Also... page 534 of the FPGA datasheet you sent me has this to say:

>Dependency: This register [DEACHINT] is available in device mode and only when parameter''OTG_MULTI_PROC_INTRPT''

So it looks like you're right about the multi-core thing you say above.

I guess my original question is resolved, but I might post other stuff relevant to the STM USB in this thread.  Does that make sense, or do you want to move to a new thread?

Posted on November 30, 2016 at 09:20

> Found it!  Thank you.  Hopefully the gecko docs will help.

Having seen it, I doubt.

> In the mean time, are you aware of any public Synopsis docs?

No. I believe the real stuff comes with purchasing the IP (together with the confidentiality clauses). It would be very surprising - and, honestly, unwise - if Synopsis would not refer all requests for support from the end users to the implementor.

> A similar figure appears in the STM32F74xxxx docs on page 1322.

Ah, indeed... Thanks. I've looked at the analogous figure (f.394) in 'F4's OTG_FS module and that's simpler (nor is there the DEACHINT register itself). The _HS has it indeed.... I never understood the reason for two chapters for one IP, albeit differently configured - and apparently ST realized that it's not a good idea by the time they arrived at the F7s (they still did not realize it for the TIM chapters, though... ;) )

> I guess my original question is resolved, but I might post other stuff relevant to the STM USB in this thread.  Does that make sense, or do you want to move to a new thread?

I'd selfishly prefer you to post them in *my* thread... ;)

Jan