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John F.
John F.
Associate III
April 23, 2010
Question

STM32 Software Reset

  • April 23, 2010
  • 10 replies
  • 2128 views
Posted on April 23, 2010 at 13:54

STM32 Software Reset

    This topic has been closed for replies.

    10 replies

    John F.
    John F.Author
    Associate III
    May 17, 2011
    Posted on May 17, 2011 at 13:48

    Hi Clive, sorry for delay in replying.

    You're right! It's hidden in core_cm3.h as the following in Release 3.1.2,

    static __INLINE void NVIC_SystemReset(void)

    {

      SCB->AIRCR  = (NVIC_AIRCR_VECTKEY | (SCB->AIRCR & (0x700)) | (1<<NVIC_SYSRESETREQ)); /* Keep priority group unchanged */

      __DSB();                                                                             /* Ensure completion of memory access */             

      while(1);                                                                            /* wait until reset */

    }

    and as

    static __INLINE void NVIC_SystemReset(void)

    {

      SCB->AIRCR  = ((0x5FA << SCB_AIRCR_VECTKEY_Pos)      |

                     (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |

                     SCB_AIRCR_SYSRESETREQ_Msk);                   /* Keep priority group unchanged */

      __DSB();                                                     /* Ensure completion of memory access */             

      while(1);                                                    /* wait until reset */

    }

    in Release 3.2.0

    Adds __DSB() and while(1) wait to your code.

    Not sure why they're different. Do you know?

    John F.

    Tesla DeLorean
    Tesla DeLorean
    Guru
    May 17, 2011
    Posted on May 17, 2011 at 13:48

    They probably just changed the name. It was in the library source file stm32f10x_nvic.c

    #define AIRCR_VECTKEY_MASK    ((u32)0x05FA0000)

    /*******************************************************************************

    * Function Name  : NVIC_GenerateSystemReset

    * Description    : Generates a system reset.

    * Input          : None

    * Output         : None

    * Return         : None

    *******************************************************************************/

    void NVIC_GenerateSystemReset(void)

    {

      SCB->AIRCR = AIRCR_VECTKEY_MASK | (u32)0x04;

    }

    or

        ldr     r0,=0xE000ED0C ; SCB AIRCR

        ldr     r1,=0x05FA0004

        str     r1, [r0, #0]

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    glory_man
    glory_man
    Associate III
    December 27, 2011
    Posted on December 27, 2011 at 13:19

    I use stm32f407. Is it possible reset cpu while debugger is running ?

    I tried to reset cpu after can-frame is received with NVIC_SystemReset(). But after this function calling debugger jumped to HardFault_Handler(void). Am I missed something ?

    Tesla DeLorean
    Tesla DeLorean
    Guru
    December 27, 2011
    Posted on December 27, 2011 at 14:13

    I suspect the debugger being used might impact things, as will how the code is being run (ie User/System, RAM/FLASH). Presumably the debugger permits you to examine registers, memory and stack, to better understand/describe the failure.

    What instruction/register is Hard Faulting? Don't know, then you'll need to use a Hard Fault handler that can decompose the faulting state rather than a while(1);

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    glory_man
    glory_man
    Associate III
    December 27, 2011
    Posted on December 27, 2011 at 14:48

    I read fault registers inside faulting handler function. HFSR = 0x40000000, DFSR = 0x9, CFSR = 0x400. What does it mean ? What registers I need to examine else ?

    glory_man
    glory_man
    Associate III
    December 28, 2011
    Posted on December 28, 2011 at 07:36

    This is strange. It seems like fault expected after previous command execution - write data to memory at 0x2000FFFF. As far as I understand fsr-register state talked - ''Imprecise data access error''. But this addr is in RAM memory range.

    glory_man
    glory_man
    Associate III
    January 24, 2012
    Posted on January 24, 2012 at 09:51

    Is it possible to detect address of ''hard-faulting instruction '' ?

    As far as I understand there is a set of status registers. MMFAR, BFAR - stores faulting address - associated with the attempted access. But this is accessed address not faulting instruction.

    Is there register stored hard-faulting instruction address?

    Tesla DeLorean
    Tesla DeLorean
    Guru
    January 24, 2012
    Posted on January 24, 2012 at 14:19

    It stores several registers on the stack, Joseph Yiu published an example in his Cortex M3 book. If your stack pointers are broken, this could be problematic.

    An imprecise fault suggests an earlier write exiting the write buffer.

    See this example Frank put together.

    http://blog.frankvh.com/2011/12/07/cortex-m3-m4-hard-fault-handler/

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    glory_man
    glory_man
    Associate III
    January 30, 2012
    Posted on January 30, 2012 at 08:59

    I added asm-code for hard_fault function.

    But when hard fault occurred program stopped on first line TST LR,#4. Next instruction ITE EQ does not execute. Why? I cann't understand. LR=0xfffffffd. What does it mean?

    Tesla DeLorean
    Tesla DeLorean
    Guru
    January 30, 2012
    Posted on January 30, 2012 at 14:16

    LR contains a magic value, not a program counter. It infers which stack is in use, and allows the core to return from the faulting state. For more information refer to the core documentation.

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