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Fristedt.Jan
Fristedt.Jan
Associate III
April 28, 2014
Question

STM32F407 TEIF DMA transfer error interrupt

  • April 28, 2014
  • 6 replies
  • 2092 views
Posted on April 28, 2014 at 19:47

Hi all,

I have searched and this is the only (relevant) hit I get:

https://my.st.com/public/STe2ecommunities/mcu/Lists/cortex_mx_stm32/DMA%20issue%20-%20transfer%20error%20flag%20TEIF

Unfortunately I have an application were I want to use DMA for data transfer. ADC2 is sampled and data is put into internal RAM, decimated etc and then finally moved to external SRAM (FSMC). At times data is copied back into internal RAM to do some calculations (FFT etc) and then results are moved to external SRAM.

My problem is that earlier, when I only used DMA for transfer from ADC to internal RAM and occasionally out to and in from external SRAM everything SEEMED to be OK. Today I tried to change all data moves to DMA to save CPU cycles. Unfortunately I get TEIF errors both if I use interrupts for DMA and polling. Only transfer errors, never any transfer completes.

I read the errata and found something about problems with DMA2 in section 2.1.10. As I read it, it is no explanation to my problem. But what do I know?

Questions:

Anyone that recognise this problem?

Is there a solution? All ADCs use DMA2, all memory to memory use DMA2.

Is this section 2.1.10 related to my problem?

TIA!

#teif
    This topic has been closed for replies.

    6 replies

    waclawek.jan
    waclawek.jan
    Super User
    April 28, 2014
    Posted on April 28, 2014 at 20:10

    Which DMA/channel?

    Read out this channel's registers (plus LISR/HISR) at the moment when the error occurs (in the ISR), and post here.

    JW
    Fristedt.Jan
    Fristedt.JanAuthor
    Associate III
    April 28, 2014
    Posted on April 28, 2014 at 21:34

    I have checked LISR, and TEIF is active. The control register is set up in the same way as in the other working(?) function. Unfortunately I don't have access to the settings at the moment. By the way, I found a note with the vaalue of the stream control register, it's 0x00025694.

    Fristedt.Jan
    Fristedt.JanAuthor
    Associate III
    April 29, 2014
    Posted on April 29, 2014 at 12:22

    Hi Jan (nice name),

    I have attached a file with the content of the DMA registers and the code involved. If you find an obvious mistake I will be very glad.

    TIA!

    waclawek.jan
    waclawek.jan
    Super User
    April 29, 2014
    Posted on April 29, 2014 at 12:50

    OK, so this one was easy.

    > This is the register contents when I break where i read the LISR:

    > 0x40026400  00300008 00000000 00000000 00000000 00025694 0000001F 10004418 640C0600

    > 0x40026420  00000000 00000024

    i.e. S0PAR = 0x10004418 - you can't DMA from/into CCM in STM32F4xx.

    JW

    Fristedt.Jan
    Fristedt.JanAuthor
    Associate III
    April 29, 2014
    Posted on April 29, 2014 at 13:01

    Thank you VERY VERY MUCH! The declaration of the buffers were missing ''__attribute__((section(''.buf'')))'' so they ended up in ''.bss''. I would have found out eventually but you know how it is, stare enough at a problem and you can't see the problem. The only odd thing I saw about the address 0x10004418 was that it ended in 18. A bit odd if you have a section only for buffers.

    Once again, THANK YOU!

    /Jan

    waclawek.jan
    waclawek.jan
    Super User
    April 29, 2014
    Posted on April 29, 2014 at 13:25

    > but you know how it is, stare enough at a problem and you can't see the problem.

    I know.

    Guess why did I know what to look for... ;)

    Jan

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