VDDA starts after VDD

Posted on July 20, 2015 at 14:55

I can't find your quote with a search of this reference. Please provide section number and paragraph.

In the F405 data sheet, the following information provides guidance. Check the data sheet for your processor of interest.

''It is recommended to power VDD and VDDA from the same source. A maximum difference of 300 mV between VDD and VDDA can be tolerated during power-up and power-down operation.''

Cheers, Hal

Posted on July 20, 2015 at 17:20

Sorry, AN4080, Page 6:

...

The VDDA voltage level must always be greater than or equal to the VDD voltage level

and must be provided first.

...

What about startup/power on in this case?

To the previous questions, one more:

    Now after the knowledge from AN4080. What will happen if VDDA fall down and VDD is OK.

Posted on July 20, 2015 at 17:43

If it thresholds the POR, then the NRST is going to be clamped low for a period as described in the manual. The manual and not the App Note is the controlling documentation.

If you can't control the VDD/VDDA with respect to each other, then I'd suggest you threshold both with external POR circuits that clamp NRST low for a 100ms or so, that way both attain stable operating levels before the processor, and code execution, is permitted to start.

Posted on July 20, 2015 at 17:49

Now after the knowledge from AN4080. What will happen if VDDA fall down and VDD is OK.

That same page 6 lists the functionality that will be lost. Don't know if anything will be damaged.

ST's guidance is to use the same source for Vdd and Vdda, and add additional filtering to Vdda to reduce ADC and DAC conversion noise. If you are doing something different, I suspect you may be on your own.

Cheers, Hal

Posted on July 20, 2015 at 18:11

...Don't know if anything will be damaged....

That is my question.

I have an LDO on VDDA. Theoretically it can:

 start later than VDD

 can fall down anytime

Posted on July 20, 2015 at 18:21

Going to cause the VCO/PLL/HSE/HSI to FAIL, or become unstable, and if it gets sufficient low the processor will be held in reset.

I don't expect gray smoke, but you will get undesirable operation...

Posted on July 20, 2015 at 18:27

>>Going to cause the VCO/PLL/HSE/HSI to FAIL.

Does it mean that I can't trust an internal watchdog in that case and I have to solve it external on the board?

Posted on July 20, 2015 at 18:57

For STM32F415...(data sheet STM32F415xx STM32F417xx) I could not find the time constraint, mentioned above. Do I need to take care about the time constraint on STM32F415?

Only a following restriction:

 It is recommended to power VDD and VDDA from the same source. A maximum difference of 300 mV between VDD and VDDA can be tolerated during power-up and power-down operation.

Posted on July 20, 2015 at 19:04

Well you're entering a whole domain of unknown/unspecifed behaviour.

If you're supplies are going to do weird and uncontrollable things, then yes you're going to have to do something that implements some rational/defined behaviour externally.

Some very simple POR chips on each of the supplies enforcing a specific and common threshold, should hold the STM32 in reset when things are outside the operation envelope.

Remember the bulk of the silicon on the STM32 is running at 1.25V

Posted on July 20, 2015 at 19:22

What time constraint? I said I liked 100ms. The STM32F4 POR has a minimum ~20us pulse width. I think that's a bit tight for sloppy external RC reset circuits, or supplies with ridiculous rise times between 1.2 and 2.7 V.

I suspect the 300mV comes from the fact there will be some internal conduction paths. Things aren't supposed to be powered that way, but might find a path, whether it's through internal or external parts.

I'm not sure you're going to get ST engineers with familiarity of the silicon at this level answering on the forum.