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mehmet.karakaya
mehmet.karakaya
Associate III
September 6, 2014
Question

F103 HSI instead of HSE

  • September 6, 2014
  • 1 reply
  • 537 views
Posted on September 06, 2014 at 17:52

hello dear forum,

I have changed F103 on the motherboard - however, HSE doesnot start up but I can download code into the F103 with USART I dont want to throw away the board my question which lines to change how at the below startup code ? for using HSI instead of HSE thank you 

void
SetSysClockTo72(
void
)
{
/* SYSCLK, HCLK, PCLK2 and PCLK1 configuration -----------------------------*/
/* RCC system reset(for debug purpose) */
RCC_DeInit();
/* Enable HSE */
RCC_HSEConfig(RCC_HSE_ON);
/* Wait till HSE is ready */
HSEStartUpStatus = RCC_WaitForHSEStartUp();
if
(HSEStartUpStatus == SUCCESS)
{
/* Enable Prefetch Buffer */
FLASH_PrefetchBufferCmd(FLASH_PrefetchBuffer_Enable);
/* Flash 2 wait state */
FLASH_SetLatency(FLASH_Latency_2);
/* HCLK = SYSCLK */
RCC_HCLKConfig(RCC_SYSCLK_Div1); 
/* PCLK2 = HCLK */
RCC_PCLK2Config(RCC_HCLK_Div1); 
/* PCLK1 = HCLK/2 */
RCC_PCLK1Config(RCC_HCLK_Div2);
/* ADCCLK = PCLK2/4 */
RCC_ADCCLKConfig(RCC_PCLK2_Div6); 
//#else
/* PLLCLK = 8MHz * 9 = 72 MHz */
RCC_PLLConfig(RCC_PLLSource_HSE_Div1, RCC_PLLMul_9);
//#endif
/* Enable PLL */
RCC_PLLCmd(ENABLE);
/* Wait till PLL is ready */
while
(RCC_GetFlagStatus(RCC_FLAG_PLLRDY) == RESET)
{
}
/* Select PLL as system clock source */
RCC_SYSCLKConfig(RCC_SYSCLKSource_PLLCLK);
/* Wait till PLL is used as system clock source */
while
(RCC_GetSYSCLKSource() != 0x08)
{
}
}
else
{ 
/* If HSE fails to start-up, the application will have wrong clock configuration.
User can add here some code to deal with this error */
/* Go to infinite loop */
while
(1)
{
}
}
}

#hsi-f103
This topic has been closed for replies.

1 reply

zzdz2
zzdz2
Associate
September 7, 2014
Posted on September 07, 2014 at 19:08

I use following function, you can just remove those lines where hse>0 (hse==0 means HSI) 

static void initclock(uint8_t mhz, uint8_t hse)
{
#define CLOCK_HSI_MZH 4
if (hse > 0)
mhz /= hse;
else
mhz /= CLOCK_HSI_MZH;
if (mhz < 
2
)
mhz
= 
2
;
if (hse > 0)
mhz *= hse;
else
mhz *= CLOCK_HSI_MZH;
g_clkmhz = mhz;
RCC->CR |= RCC_CR_HSION;
/* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
RCC->CFGR &= (uint32_t) 0xF0FF0000;
/* Reset HSEON, CSSON and PLLON bits */
RCC->CR &= (uint32_t) 0xFEF6FFFF;
/* Reset HSEBYP bit */
RCC->CR &= (uint32_t) 0xFFFBFFFF;
/* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
RCC->CFGR &= (uint32_t) 0xFF80FFFF;
/* Disable all interrupts and clear pending bits */
RCC->CIR = 0x009F0000;
#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
/* Reset CFGR2 register */
RCC->CFGR2 = 0x00000000;
#endif
//SetSysClock();:
#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL 
/* Enable Prefetch Buffer */
FLASH->ACR |= FLASH_ACR_PRFTBE;
/* Flash 0 wait state */
FLASH->ACR &= (uint32_t) ((uint32_t) ~ FLASH_ACR_LATENCY);
if (mhz <= 24)
FLASH->ACR |= (uint32_t) FLASH_ACR_LATENCY_0;
else if (mhz <= 48)
FLASH->ACR |= (uint32_t) FLASH_ACR_LATENCY_1;
else
FLASH->ACR |= (uint32_t) FLASH_ACR_LATENCY_2;
#endif
/* HCLK = SYSCLK */
RCC->CFGR |= (uint32_t) RCC_CFGR_HPRE_DIV1;
/* PCLK2 = HCLK */
RCC->CFGR |= (uint32_t) RCC_CFGR_PPRE2_DIV1;
/* PCLK1 = HCLK (/2) */
if (mhz <= 36)
RCC->CFGR |= (uint32_t) RCC_CFGR_PPRE1_DIV1;
else
RCC->CFGR |= (uint32_t) RCC_CFGR_PPRE1_DIV2;
// dafault clock:
if ((mhz == 8) && (!hse))
return;
RCC->CFGR &= (uint32_t) ~ (RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE
| RCC_CFGR_PLLMULL);
/* PLL configuration: */
if (hse > 0)
{
// HSE:
uint32_t waitcnt = 100;
/* Enable HSE */
RCC->CR |= RCC_CR_HSEON;
/* Wait till HSE is ready and if Time out is reached exit */
while (!(RCC->CR & RCC_CR_HSERDY))
{
sleep(10000);
if (!--waitcnt)
goto hsi;
};
#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
RCC->CFGR |= RCC_CFGR_PLLSRC_PREDIV1
| (RCC_CFGR_PLLMULL3 * ((mhz / hse) - 2));
#else
RCC->CFGR |= RCC_CFGR_PLLSRC_HSE
| (RCC_CFGR_PLLMULL3 * ((mhz / hse) - 2));
#endif
}
else
{
// HSI:
hsi:
RCC->CFGR |= RCC_CFGR_PLLSRC_HSI_Div2
| (RCC_CFGR_PLLMULL3 * ((mhz / CLOCK_HSI_MZH) - 2));
}
/* Enable PLL */
RCC->CR |= RCC_CR_PLLON;
/* Wait till PLL is ready */
while ((RCC->CR & RCC_CR_PLLRDY) == 0)
{
}
/* Select PLL as system clock source */
RCC->CFGR &= (uint32_t) ((uint32_t) ~ (RCC_CFGR_SW));
RCC->CFGR |= (uint32_t) RCC_CFGR_SW_PLL;
/* Wait till PLL is used as system clock source */
while ((RCC->CFGR & (uint32_t) RCC_CFGR_SWS) != (uint32_t) 0x08)
{
}
}

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