cannot use pll stm32f103rb

Posted on April 17, 2011 at 16:01

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Guru

Posted on May 17, 2011 at 14:31

Printing out the RCC registers in your two conditions might be instructive to understand how the PLL is running at the different speeds.

This line makes a lot of assumptions

// Select PREDIV1 as PLL source and sett PLL mul to 3 (set bit 0)

// for 8*3 = 24 MHz

RCC->CFGR |= RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL_0;

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ezrabAuthor

Associate III

Posted on May 17, 2011 at 14:31

but isnt this line disable all assumation?

''

/* Select PLL as system clock source */

RCC->CFGR = (RCC->CFGR & ~RCC_CFGR_SW) | RCC_CFGR_SW_PLL;

''

Guru

Posted on May 17, 2011 at 14:31

Perhaps you shouldn't be making presumptions about the initial condition of RCC->CFGR

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