Skip to main content
Uwe Bonnes
Uwe Bonnes
Chief
March 6, 2015
Question

SWD clock restrictions

  • March 6, 2015
  • 3 replies
  • 1533 views
Posted on March 06, 2015 at 11:33

Hello,

the STM32 datasheets do not mention any restictions on SWD or JTAG frequency. Some ''internet knowledge'' tells that older ARM cores had a HCLK/6 limitation on SWD/JTAG clock frequency. Has anybody hard facts for Cortex-M and/or STM32?

Thanks

#swclk-limits
    This topic has been closed for replies.

    3 replies

    Tesla DeLorean
    Tesla DeLorean
    Guru
    March 6, 2015
    Posted on March 06, 2015 at 11:54

    You'd need something pretty exotic to drive it. You might want to ask on an ARM silicon leaning forum. The pins top out at 100 MHz, I'd expect 40-50 MHz to be possible.

    http://www.keil.com/ulinkpro/

    http://www.arm.com/products/system-ip/debug-trace/coresight-soc-components/serial-wire-debug.php

    Tips, Buy me a coffee, or three.. PayPal Venmo (See Profile) Up vote any posts that you find helpful, it shows what's working..
    Uwe Bonnes
    Uwe BonnesAuthor
    Chief
    March 6, 2015
    Posted on March 06, 2015 at 12:43

    So you postulate that there is no miminum relation between HCLK and SWCLK?

    Tesla DeLorean
    Tesla DeLorean
    Guru
    March 6, 2015
    Posted on March 06, 2015 at 14:52

    You'd want to find yourself someone familiar with the debug unit implementation, either at ARM or ST, start by pushing in via an FAE.

    I'd expect there to be a synchronizer somewhere, which will likely limit you to some fraction of the primary clock, that you're not synchronous with. The logic involved in the shifting is almost certainly capable of >200MHz in an F4.

    I don't think it would be that hard to determine where the gears start grinding.

    Tips, Buy me a coffee, or three.. PayPal Venmo (See Profile) Up vote any posts that you find helpful, it shows what's working..
      Terms & ConditionsAccessibility statement