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whg03
whg03
Associate
June 23, 2014
Question

STM32Cube stack alignment problem?

  • June 23, 2014
  • 4 replies
  • 1296 views
Posted on June 23, 2014 at 14:34

STM32Cube ld scripts set _estack to the last location of RAM like this: 

/* Highest address of the user mode stack */
_estack = 0x20017FFF; /* end of RAM */

I had several problems with code that uses doubles. Here is an example of printf which converts float arguments to double. 

float flt = 1.234;
printf(''flt: %f\n'', flt);
double dbl = 9.8765;
printf(''dbl: %f\n'', dbl);

This code prints this: 

flt: -2.000000
dbl: -0.000000

If I change the definition of _estack like this: 

/* Highest address of the user mode stack */
_estack = 0x20018000; /* end of RAM */

I get the correct result: 

flt: 1.234000
dbl: 9.876500

Is this ld script wrong? Many other Cube projects have similar values for _estack. I thought _estack should be aligned on an 8 byte boundary. Is this correct? This example is for the ld script STM32F401RE_FLASH.ld for a Nucleo project.
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    4 replies

    Tesla DeLorean
    Tesla DeLorean
    Guru
    June 23, 2014
    Posted on June 23, 2014 at 14:58 

    _estack = 0x20017FFF;

    Yes, that does look pretty ridiculous. 4-byte alignment should be fine, you don't have anything that can atomically read a 64-bit value, and there is no caching or wide buses.
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    whg03
    whg03Author
    Associate
    June 23, 2014
    Posted on June 23, 2014 at 15:42

    Does this apply for libraries? 

    The Application Binary Interface (ABI) for the ARM architecture requires that the stack must
be eight-byte aligned on all external interfaces, such as calls between functions in different
source files. However, code does not need to maintain eight-byte stack alignment internally, for
example in leaf functions.

    Tesla DeLorean
    Tesla DeLorean
    Guru
    June 23, 2014
    Posted on June 23, 2014 at 17:14

    That would depend a lot on what version of the ABI they were compiled against. The goal posts have been moved because other ARM architectures can read 64-bit, or have buses/caches wide enough to support that. I don't see this being an issue on M0/M3/M4 designs, and the FPU doesn't support doubles.

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    whg03
    whg03Author
    Associate
    June 23, 2014
    Posted on June 23, 2014 at 18:52

    I was reading about Cortex M3. Here is the next paragraph: 

    This means that when an interrupt or exception occurs the stack might not be correctly
eight-byte aligned. Revision 1 and later of the Cortex-M3 silicon can automatically align the
stack pointer when an exception occurs. This behavior must be enabled by setting STKALIGN (bit
9) in the Configuration Control Register at address 0xE000ED

    Looks like I need to do more reading.
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