Associate II

Question

M0 GPIO with DMA max speed ?

Forum|Forum|11 years ago
April 16, 2015
10 replies
3072 views

Posted on April 16, 2015 at 14:46

Hi, I'm using an stm32f072 part, trying to toggle 8 GPIO pins with DMA from memory.

The DMA is plugged to a Timer (2) update event which has 48MHz using HSI48 (no crystal for now).

I have two issues currently :

- HSI48 seems to take a long time starting (well, registers say it starts quite fast but if I don't want a fault on GPIO setup I need to setup an empty loop (like for (volatile i=0;i<1000;i++); ) . Is this expected or is there an issue ? For space reasons I'm using CMSIS directly. But this one is not blocking.

- I achieve to output around 8MHz toggle speed (not exact value), but if I reduce the ARR value of Timer2, the GPIO toggle speed don't seem to be less than that.

Is it actually possible to toggle GPIOs with DMA faster than that ? Would 12MHz be possible (chip main clock is 48MHz) ? Is there something to be wary of (using HSI, HSE ; different DMA event ... ) ? I can post the init code (CMSIS) if needed.

thanks a lot for your help, I tried to scout google and rereading the refman with no luck. Any ideas ?

#gpio #dma #stm32f0

This topic has been closed for replies.

xavier2399Author

Associate II

Posted on April 16, 2015 at 16:31

but if I reduce the ARR value of Timer2, the GPIO toggle speed don't seem to be less than that.

Sorry, clarification : I cannot get speed higher than 8MHz approx, even if I get the ARR value lower (and thus UP events from the timer to the DMA more frequently).

waclawek.jan

Super User

Posted on April 16, 2015 at 16:56

> I cannot get speed higher than 8MHz approx,

That's 3 cycles per pins' state change/DMA transfer - one cycle source read, one cycle target write, one cycle arbitration/housekeeping/whatever. I wouldn't expect less.

JW

xavier2399Author

Associate II

Posted on April 16, 2015 at 17:31

Thanks for your answer.

I don't understand, because:

- if the main clock is 48MHz, 3 cycles would be 16MHz;

- 4 cycles is 12MHz (my goal).

- We're talking about 8MHz here, so it's 6 cycles.

Can I expect less ?

Tesla DeLorean

Guru

Posted on April 16, 2015 at 17:37

If Google doesn't give you answers sometimes you need to be a pioneer.

At some point you'll saturate the processor, and it won't do any useful work, consider a more appropriate solutions/parts.

Consider if a mem-to-mem DMA works without a timer, or what a tight loop outputting alternating data, this should get you an upper limit on what might be possible.

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xavier2399Author

Associate II

Posted on April 16, 2015 at 17:39

(dupe, sorry)

xavier2399Author

Associate II

Posted on April 16, 2015 at 17:46

> If Google doesn't give you answers sometimes you need to be a pioneer.

sure, I just wanted to stress that I did my homework (sort of)

>At some point you'll saturate the processor, and it won't do any useful work, consider a more appropriate solutions/parts.

does the DMA not leave some bus bandwith free for the CPU ?

>Consider if a mem-to-mem DMA works without a timer, or what a tight loop outputting alternating data, this should get you an upper limit on what might be possible.

Ah yes. I didn't realize that Mem2Mem DMA could work with GPIO.

waclawek.jan

Super User

Posted on April 16, 2015 at 18:08

> I don't understand

f=1/period

period consists of TWO transitions

JW

Tesla DeLorean

Guru

Posted on April 16, 2015 at 18:29

> If Google doesn't give you answers sometimes you need to be a pioneer.

sure, I just wanted to stress that I did my homework (sort of)

It was more of a suggestion to pull up your sleeves and figure it out.

Some time the available examples and documentation fail to illustrate all outcomes, at that point you need to infer information, and test the physical limits manually.

Timers always half things from the get-go.

M2M may be an option, I'm not using these parts.

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xavier2399Author

Associate II

Posted on April 17, 2015 at 14:37

> It was more of a suggestion to pull up your sleeves and figure it out.

Ah yes, which is where I'm stuck at 8Mhz on a 48MHz with a DMA .. aiming at 12.

With a cortex M4 @168 I can do 26MHz (tested), and I guess you could go further.

(Overclocking does not seem to work at all).

> Timers always half things from the get-go.

OK, but it does not seem to be the issue since I can change ARR from 4 to 6 and it does not change the output frequency, that's what was curious for me. I understand being limited by a rate but there it seems the timer frequency cannot be below a certain limit ??

> M2M may be an option, I'm not using these parts.

I tried M2M, but it does not seem to improve things - I need to re-check however, and bitbanging with CPU .

Well if it does not work I could also go with a 302@72MHz or 100MHz chip ... if it changes anything : I found this :

https://vjordan.info/log/fpga/stm32-bare-metal-start-up-and-real-bit-banging-speed.html

, but he only seems to get 3.6MHz on a 72MHz chip which I find strange.

Tesla DeLorean

Guru

Posted on April 17, 2015 at 15:16

But as I recall the F1 series had the GPIO's attached to the APB, not the AHB. An the flash slows execution speed.

I'm not sure banging a GPIO up and down in a pipelined processor, with write buffers, and disparate bus speeds to be an effective test of processor performance.

Putting patterns on a bus would at 10's of MHz would seem like a job better suited to programmable logic, or state machines wired to ROMs.

At some point you're going to hit a bandwidth wall, half your cycles reading, half writing, and your processor stalled out.

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