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john doe
john doe
Senior III
August 2, 2017
Question

TIMx_SMCR->SMS - 3 bits or 4?

  • August 2, 2017
  • 4 replies
  • 959 views
Posted on August 02, 2017 at 19:28

RM0351, section 31.4.3 slave mode control register.

chart shows SMS[2:0] but the description of SMS on page 1032 describes a 4 bit number

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    4 replies

    waclawek.jan
    waclawek.jan
    Super User
    August 2, 2017
    Posted on August 02, 2017 at 19:34

     
    john doe
    john doeAuthor
    Senior III
    August 3, 2017
    Posted on August 03, 2017 at 01:36

     ,

     ,

    0690X00000607rpQAA.png

    Dopey me. That SMS[3] is the fourth bit. They even made it easy in the header file

    ♯ define TIM_SMCR_SMS_Pos , , , , , , , , , (0U) , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , ,  ,

     ,

    ♯ define TIM_SMCR_SMS_Msk , , , , , , , , , (0x10007U <,<, TIM_SMCR_SMS_Pos) , , , , , , , , , , , , , , /*!<, 0x00010007 */

     ,

    ♯ define TIM_SMCR_SMS , , , , , , , , , , , , , TIM_SMCR_SMS_Msk , , , , , , , , , , , , , , , , , , , , , , , , , , , , /*!<,SMS[2:0] bits (Slave mode selection) */

     ,

    ♯ define TIM_SMCR_SMS_0 , , , , , , , , , , , (0x00001U <,<, TIM_SMCR_SMS_Pos) , , , , , , , , , , , , , , /*!<, 0x00000001 */

     ,

    ♯ define TIM_SMCR_SMS_1 , , , , , , , , , , , (0x00002U <,<, TIM_SMCR_SMS_Pos) , , , , , , , , , , , , , , /*!<, 0x00000002 */

     ,

    ♯ define TIM_SMCR_SMS_2 , , , , , , , , , , , (0x00004U <,<, TIM_SMCR_SMS_Pos) , , , , , , , , , , , , , , /*!<, 0x00000004 */

     ,

    ♯ define TIM_SMCR_SMS_3 , , , , , , , , , , , (0x10000U <,<, TIM_SMCR_SMS_Pos) , , , , , , , , , , , , , , /*!<, 0x00010000 */

    this is how I ended up working around:

     , , switch(((*(uint32_t*)&,TIM3->,SMCR &, TIM_SMCR_SMS) >,>, TIM_SMCR_SMS_Pos) )

     ,

     , , {

     ,

     , , case 0b00000000000000000000000000000000: printf(''Slave mode disabled\r\n''), break,

     ,

     , , case 0b00000000000000000000000000000001: printf(''Encoder mode 1\r\n''), break,

     ,

     , , case 0b00000000000000000000000000000010: printf(''Encoder mode 2\r\n''), break,

     ,

     , , case 0b00000000000000000000000000000011: printf(''Encoder mode 3\r\n''), break,

     ,

     , , case 0b00000000000000000000000000000100: printf(''Reset mode\r\n''), break,

     ,

     , , case 0b00000000000000000000000000000101: printf(''Gated mode\r\n''), break,

     ,

     , , case 0b00000000000000000000000000000110: printf(''Trigger mode\r\n''), break,

     ,

     , , case 0b00000000000000000000000000000111: printf(''External clock mode 1\r\n''), break,

     ,

     , , case 0b00000000000000010000000000000000: printf(''Combined reset + trigger mode\r\n''), break,

     ,

     , , }
    waclawek.jan
    waclawek.jan
    Super User
    August 4, 2017
    Posted on August 04, 2017 at 10:09

    Btw. the same applies for TIMx_CCMRy.OCzM  - the OCzM[3] bit is further up in the same register.

    JW

    Amel NASRI
    Amel NASRI
    ST Technical Moderator
    August 4, 2017
    Posted on August 04, 2017 at 17:00

    Hi

    doe.john.016

    ‌,

    A request is raised internally to add a note saying that the other bit is described as standalone in the same register.

    Thanks

    Waclawek.Jan

    ‌ for your proposal.

    -Amel

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