Question
F2/F4 I2S Ext.Clock
Posted on April 03, 2013 at 14:19
Hi friends,
It is written at ref/man for F2 and F4:Bit 7:0 I2SDIV: I2S Linear prescaler
I2SDIV [7:0] = 0 or I2SDIV [7:0] = 1 are forbidden values. Why ''0'' is forbidden is clear, but why ''1'' ?! I make some intensive tests, and with I2SDIV=1 it works fine, did not see any problem. Usially, I not like to use the components ''out of spec'', for clear reason, but I want to understand the spec. This issue I don't understant, so I have to decide - or use it out of spec, or to double the clock frequency Ithat increase the device' cost). Mayby DIV=1 has a problem only with internal PLL clock? Thanks. #stm32-i2s