AutoPolling QSPI and memory erase

Posted on February 16, 2018 at 19:52

Hello friends.

I have a problem. I erase external memory. But this procedure last long time. So I set autopolling mode with interrupt. But It doesn't work.

When I send erase command I need wait on WIP bit in status register. And when QIP bit is set, I need generate interrupt.

And program work:

1. Send 0x06 - enable write to memory
2. Send erase memory 0xC7
3. Set autopolling mode

And when I set autopolling mode, immediately is generating interrupt. And it is wrong.

Any idea, what is wrong?

So. Here is my autopolling initializion.

void QSPI_AutoPollingMemReady(void)

{

uint32_t tmpreg = 0;

while (QUADSPI->SR & QUADSPI_SR_BUSY) {};

QUADSPI->PSMAR = 0x0000;

QUADSPI->PSMKR = 0x0101;

QUADSPI->CR &= ~ QUADSPI_CR_PMM; /* AND Match Mode */

QUADSPI->CR |= QUADSPI_CR_APMS; //enable autopolling

QUADSPI->DLR = 0x00; //data lenght 0-1bytes; 1-2bytes; 2-3bytes.....

tmpreg = QUADSPI->CCR;

tmpreg &= 0x90800000;

tmpreg |=

(0x00 << QUADSPI_CCR_DDRM_Pos) | // Disable DDR mode

(0x00 << QUADSPI_CCR_DHHC_Pos) | // Delay the data output using analog delay

(0x00 << QUADSPI_CCR_SIOO_Pos) | // Send instruction on every transaction

(0x02 << QUADSPI_CCR_FMODE_Pos) | // function QSPI (0-indirect write); (1-indirect read); (2-autopolling)

(0x01 << QUADSPI_CCR_DMODE_Pos) | // Data mode (0-nodata); (1-data on single line); .....

(0x00 << QUADSPI_CCR_DCYC_Pos) | // Dummy cycle

(0x00 << QUADSPI_CCR_ABSIZE_Pos) | // size of alternate bytes (0-8bit); (1-16bit); (2-24bit); (3-32bit)

(0x00 << QUADSPI_CCR_ABMODE_Pos) | // Alternate mode (0-no alternate); (1-alternate on single line)

(0x02 << QUADSPI_CCR_ADSIZE_Pos) | // size of address bytes (0-8bit); (1-16bit); (2-24bit); (3-32bit)

(0x00 << QUADSPI_CCR_ADMODE_Pos) | // Address mode (0-no address); (1-address on a single line)

(0x01 << QUADSPI_CCR_IMODE_Pos ) | // Instruction mode (0-no instruction); (1-instruction on signel line)

(READ_STATUS_REG_CMD << QUADSPI_CCR_INSTRUCTION_Pos); // Instruction send on SPI 0x05

QUADSPI->CCR = tmpreg;

asm(''NOP'');

QUADSPI->FCR = 0x00; //clear flag

asm(''NOP'');

/*Enable Interrupts*/

tmpreg = QUADSPI->CR ;

tmpreg |= (uint32_t)((QUADSPI_CR_SMIE | QUADSPI_SR_SMF | QUADSPI_CR_FTIE | QUADSPI_SR_FTF | QUADSPI_CR_TEIE | QUADSPI_SR_TEF) & 0x001F0000);

QUADSPI->CR = tmpreg ;

}

And here is my interrupt:

void QUADSPI_IRQHandler(void)

{

if((QUADSPI->SR & QUADSPI_SR_FTF))

{

QUADSPI->FCR = (uint32_t)((QUADSPI_CR_SMIE | QUADSPI_SR_SMF) & 0x001F0000);

/* Disable the QSPI FIFO Threshold, Transfer Error and Status Match Interrupts */

QSPI_disable_IT((QUADSPI_CR_SMIE | QUADSPI_SR_SMF | QUADSPI_CR_FTIE | QUADSPI_SR_FTF | QUADSPI_CR_TEIE | QUADSPI_SR_TEF), DISABLE);

usart_puts(''\r\nErase success\r\n'');

}

LL_GPIO_TogglePin(GPIOB, GREEN);

}

#quadspi #nucleo-f767zi #stm32f767zi