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Eetu Nevalainen
Eetu Nevalainen
Associate II
January 23, 2018
Solved

Configuring DMA for SAI

  • January 23, 2018
  • 1 reply
  • 1779 views
Posted on January 23, 2018 at 17:40

Hi,

I'm trying to transfer data to SAI's fifo via DMA (memory-to-peripheral). I'm following reference manual's instructions for setting up DMA for SAI.

0690X00000609TVQAY.png

As soon as I enable the DMA channel FEIF4 (FIFO overrun/underrun) flag becomes active. After enabling the SAI2 interface and waiting few clock cycles TEIF4 (Transfer error) flag becomes active and disables the DMA channel. I've attached SAI2 A and DMA2 stream 4 register values below. I have no experience with DMA or SAI so maybe there's something wrong with the registers. If the registers seem OK could this be clock issue? Any help would be greatly appreciated. Please ask more info if you need to.

MCU: STM32F446ZE

SAI2 A REGISTERS

0690X00000609ShQAI.png

DMA2 STREAM 4 REGISTERS

0690X00000609SmQAI.png
    This topic has been closed for replies.
    Best answer by waclawek.jan
    Posted on January 23, 2018 at 18:21

    Don't set PFCTRL in DMAStream_CR - read 9.3.16  Flow controller.

    In direct mode, you should ignore the FEIF - there's an explanation somewhere in the forum why this happens but now the forum is in havoc and I'm not going to look it up.

    You may want to set the FIFO threshold somewhat higher than empty, otherwise the FIFO is effectively unused.

    Your SLOTR appears to be inconsistent: you set (by SLOTSZ =0) slot size equal to data size, yet try to shift the slot by FBOFF (it's ineffective but should be 0 nonetheless - the characteristic I2S 1-bit shift is already accomplished by setting FRCR.FSOFF=1); you set only one slot per frame in NBSLOT yet enable two in the SLOTEN bitmask. This btw violates the requirement for 'The number of slots should be even if FSDEF bit in the SAI_xFRCR register is set.'

    JW

    PS. What debugger is this? SAI_CR1.MCKDIV is misspelled as MCJDIV... :)

    1 reply

    waclawek.jan
    waclawek.janBest answer
    Super User
    January 23, 2018
    Posted on January 23, 2018 at 18:21

    Don't set PFCTRL in DMAStream_CR - read 9.3.16  Flow controller.

    In direct mode, you should ignore the FEIF - there's an explanation somewhere in the forum why this happens but now the forum is in havoc and I'm not going to look it up.

    You may want to set the FIFO threshold somewhat higher than empty, otherwise the FIFO is effectively unused.

    Your SLOTR appears to be inconsistent: you set (by SLOTSZ =0) slot size equal to data size, yet try to shift the slot by FBOFF (it's ineffective but should be 0 nonetheless - the characteristic I2S 1-bit shift is already accomplished by setting FRCR.FSOFF=1); you set only one slot per frame in NBSLOT yet enable two in the SLOTEN bitmask. This btw violates the requirement for 'The number of slots should be even if FSDEF bit in the SAI_xFRCR register is set.'

    JW

    PS. What debugger is this? SAI_CR1.MCKDIV is misspelled as MCJDIV... :)

    Eetu Nevalainen
    Eetu NevalainenAuthor
    Associate II
    January 24, 2018
    Posted on January 24, 2018 at 12:41

    Thanks! I got DMA working with your instructions. Now I have to study how slots work.

    waclawek.jan wrote:

    PS. What debugger is this? SAI_CR1.MCKDIV is misspelled as MCJDIV... :)

    The register viewer is a GNU ARM Eclipse plug-in.

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