What causes L6472 to power up / leave reset with bridges active?

[harerod]

I have designed a board with four seemingly identical motor drivers. The four L6472 are connected to an STM32-MCU via one SPI-interface, chipselect is handled by GPIO. They share a common reset signal, also GPIO. Because of the pull-downs on /STBY_RES the L6472 will only leave reset when the MCU pulls the GPIO up.

I have verified with different boards (different production runs/board revisions) and motors that U702/U703 "Wash-Selctor Valve Driver / Dilutor Valve Driver" consistently power up or leave reset with output bridges active, resulting in high current fed into the respective motors.

On the other hand, U602/U603 "XY-S-Motor-L/R" always power up as expected - with bridges in HighZ.

I can't explain this behavior from the datasheet. Would you have any recommendations?

Thanks.

[Peter BENSCH]

Welcome, @harerod​, to the community!

Is it intentional that the SW pins of U602/603 are connected to an HC14 output (U601G$4), while U702/703 are connected to the inputs of HC14 (U701G$3/4)?

Regards

/Peter

[harerod]

Hello Peter,

thanks for having a close look at this. U703-SW is externally connected to a normally closed limit switch to GND. U702-SW is connected to an Encoder Index Track, which also works as a switch to GND. To be honest - this wiring is less than ideal, thanks for finding this. The question is - would the 4k7 pull-ups to 5V inject enough current into the SW-pins to cause a malfunction?

Regards,

Marcus

[harerod]

Hello Peter,

following up on your findings, we can assume that the input level at power-up on the SW-input is different for U702/U703 than for U602/U603. Although I haven't found it spelled out in the datasheet, I could come to assume the following happens, when the L6472 leaves Reset:

• External Switch description: "By default a switch turn-on event causes a HardStop interrupt (SW_MODE bit of theCONFIG register set to ‘0’)."
• Stop commands description: "The HardStop command stops the motor instantly, ignoring deceleration constraints andmaintaining the rotor position (a holding torque is applied)."

That would at least explain the observed behavior. Of course this is less than ideal, since the "holding torque" would result in a default bridge power setting of TVAL_HOLD = 1.3125A, which is not necessarily compatible with the connected motor.

Would that be a satisfactory explanation for you?

If yes - and the if we can treat the SW-pin as a "logic input", which is rated for 5.5V max, we could close this issue.

Thank you very much,

Marcus

[Cristiana SCARAMEL]

Hi @harerod​ ,

Yes the SW pin is a logic input (AMR in Table 2: -0.3 to +5.5 V).

I confirm the SW pin behavior description (in case of SW event an HardStop command is performed and the bridges are activated with the holding torque value).

If you can measure the SW pin voltage at power on, we can verify the root cause of different behavior.

Please, click on the "Select as Best" label in the proper reply.

[harerod]

Christiana,

thank you for your confirmation. The "offending" circuits have SW activated when reset goes inactive.

I will take this information into account when redesigning the next board revision. Which will take a while, because of most semiconductors, including ST components, being unobtanium at the moment.

marcus