Two application questions for powerSTEP01 - how to externally power the core correctly and how to drive brushed DC motors?

[JMeng.1]

1. Power supply to the core logic: What is the right way to do this such that the Vs motor supply can be turned on and off while leaving the logic running? The datasheet leaves much to be desired (which are input power and output power pins is confusing). My first attempt at adding a protection diode resulted in fire coming out of the top of the dev board when the Vs was turned off. My guess is I missed something important.

2. Unrelated - there is mention online in an ST youtube video that the powerSTEP01 can be used to drive 2 brushed DC motors but I cannot locate any information about how to implement this. This would be highly desireable if there was a simple way to control PWM and direction, or closed loop current and direction (polarity).

For what it's worth, I have the powerSTEP01 successfully running on our own board with an MCU and other I/O. I like the results and performance of running in current control mode (driving NEMA34 motors with great results). It's these last issues that I'm running into dead ends on, if anyone has any insight!

[chaaalyy]

With HardHIZ command =) Of course it doesn´t "switch off" the power supply, but there´s no output to the motors anymore...

refer to https://www.st.com/content/ccc/resource/technical/document/datasheet/3f/48/e2/37/6b/ac/4c/f5/DM00090983.pdf/files/DM00090983.pdf/jcr:content/translations/en.DM00090983.pdf

and search for HIZ =) Two modes available: Soft HIZ (decelerates 1st and performs HIZ afterwards and Hard HIZ (immediately). Anyway: Be sure, not to loose steps or position in that mode...)

for 2. : i would be interested too, how to drive brushed dc motors with the ihm03a1... Two weeks ago i quickly built a servo control with two brushed dc´s, incremental encoders, controlled via step/dir signals. I just remembered, that two years ago, when i began playing around with that driver, i had one year to develop an application... 11months of that year i had to waste with the search for errors in the code, missing informations and getting no help. This time i took the quick and better way: Buying a Cytron MDD10A and after one weekend the prototype was finished :)

/Charly

[JMeng.1]

Thanks for the reply - perhaps I wasn't too clear in the first question. I am OK with the HighZ command which removes power to the motor. I am actually more interested in making sure that I can switch on and off our motor supply power (it is from a different supply than our logic) without the ST core being reset. In order for this to happen, the core can't be supplied the same way the demo boards are wired by default (using the internal regulators off of the Vs power input). There is a note about the internal ESD diodes being reversed biased in the case where Vs is off and Vcc is on, which I believe I experienced as a nice charred board.

[chaaalyy]

Ouch... It´s a long time, since i made these tests, but i think to remember, for testing the UVLO alarm, several times we provoked it with switching off the 24V for the motors... We used the ihm03a1, the 5V for the mcu and the expansion board came from an external dc-dc converter (common ground !) :( Maybe we´ve just been lucky =)

[JMeng.1]

Thanks for the idea - I purchased the X-nucleo-IHM03A1 for testing. I am supplying the 3.3V for VDD and VREG externally and connected the SPI port to an external MCU. I first drive Reset high before trying to initialize the ST registers. When the VS power is off, the SPI queries all return 0, and the FLAG/BUSY LED's remain off. Once I supply 24V to the VS for the motor supply, I can read and write the ST registers just fine.

I double checked the schematic, the 3.3V supply is driving both the VDDIO and the VREG while VCC & VS would be off & protected by external diodes in this mode.

Suspecting the oscillator wasn't running, I checked the pads at R22, (OSCOUT) pin to see if the internal oscillator had booted up... sure enough no clock until VS has power.

Reading the datasheet pg 22, the only power up conditions for the logic are as follows, so something is either wrong with the datasheet or the IC design:

7.1 Device power-up

During power-up, the device is under reset (all logic IOs disabled and power bridges in high impedance state) until the following conditions are satisfied:

• VREG is greater than VREGthOn
• Internal oscillator is operative
• STBY/RESET input is forced high.

After power-up, the device state is the following:

• Parameters are set to default
• Internal logic is driven by internal oscillator and a 2-MHz clock is provided by the OSCOUT pin
• Bridges are disabled (high impedance).
• FLAG output is forced low (UVLO failure indication).

After power-up, a period of tlogicwu must pass before applying a command to allow proper oscillator and logic startup. Any movement command makes the device exit from High Z state (HardStop and SoftStop included).

Further looking into the clock - there isn't anything mentioned about which power supply powers the internal clock (pg 29):

7.8 Internal oscillator and oscillator driver

The control logic clock can be supplied by the internal 16-MHz oscillator, an external oscillator (crystal or ceramic resonator) or a direct clock signal.

These working modes can be selected by EXT_CLK and OSC_SEL parameters in the CONFIG register (see Table 41 on page 66).

At power-up the device starts using the internal oscillator and provides a 2-MHz clock signal on the OSCOUT pin

Unfortunately I think I am at a dead end for this quest. It would have been nice to use the UVLO features and see the device from the MCU well before the VS motor power is enabled.

[JMeng.1]

For anyone else going down this route, at about 3.6VDC applied to VS & VSREG, the internal oscillator starts up but isn't stable at 2MHz until around 4VDC.

[chaaalyy]

Just had a quick look at ihm03a1 schematics...

As you said:

During power-up, the device is under reset (all logic IOs disabled and power bridges in high impedance state) until the following conditions are satisfied:

• VREG is greater than VREGthOn ...

As far, as i can see, R24 is NP, so VReg is more or less directly connected to VS (through R23) , which can be FAR higher than the stated max. 3.18V

In the datasheet it says:

VREGthOn VREG turn-on min. 2.8V typ 3V and max.3.18 V...

So i also would assume, it starts at 2.8V. If you need 4V to get it stable, i also would think, there´s definitely something wrong with the manuals :( I´m also just wondering about the behaviour, we got a couple of years ago, when we just cut off VS to provoke the UVLO. According to the datasheet, core logic should have stopped then also .... (See VREGthOff)

[JMeng.1]

Ah, but R23 is a short from VS to VSREG, not VREG.

I am measuring 3.3V on VREG and VDDIO when applied. Something still doesn't add up...

And I will stick to my original claim, this datasheet leaves a bit to be desired in terms of clarity.