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The L6472 motor driver datasheet indicates that SPI clock rise/fall times must not exceed 25nS with 30pF load. Does this mean that each L6472 presents 30pF load to SPI clock line and why is there a rise/fall time max limit??
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Hello @FFarb.1 welcome to the ST Community.
The load of 30 pF represent the test conditions for the logic.
The timings limits have the purpose to ensure that logic does not remain too long under "indeterminate" conditions.
Let me know if I clarified your doubts.
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