Skip to main content
ARaj.1
ARaj.1
Associate II
August 14, 2021
Solved

STSPIN32F0 six-step control

  • August 14, 2021
  • 9 replies
  • 2025 views

Hi, I am quoting from a previous question posted on this forum but hasn't been answered. I wanted an answer to the exact same question:

I am using the STEVAL-SPIN3201 board to control a BLDC motor.

I want to implement a position controller, so I need to hold tight the position of the rotor at a given position (1 phase to Gnd, 1 phase to pulsed Vm, and 1 floating phase).

The problem that I am encountering now, is that the Control logic gate driver embedded inside the STSPIN32F0 does not allow to set both High and Low n-channel mosfet gates at the same position (1 & 1 or 0 & 0). I understand that 1 & 1 causes a short-circuit , but I need 0 & 0 in order to set the floating phase.

Is it possible to set a floating phase on STSPIN32F0?

Thank you in advance.

This topic has been closed for replies.
Best answer by Enrico Poli

Hi @ARaj.1​ 

In my screenshot high side output is actually LOW because it is referred to OUT pin:

  • HS LOW --> GHS - OUT = 0
  • HS HIGH --> GHS - OUT = VBOOT

About your questions:

  • if input voltage is 10V, a high voltage will be 10V, high impedance will be 5V and low voltage will be 0 V?

ANS: I guess it will be probably 10 V. I guess the high impedance value will be probably 10 V.

When the output is in high impedance, it's voltage is easily biased by any leakage. In normal conditions the main leakage comes from the integrated bootstrap diode and rise the output voltage up to VREG12. If supply is 10 V, I expect VREG12 = 10 V --> VOUT = 10 V.

  • If the above is the case what is the reason for this. Why can't both high-side and low-side gates have gate voltages of 0V, why does the output have to be in high-impedance mode when both GPIO's are low

ANS: High side gate driver output must be always referred to the OUT. This because the main objective of the circuit is apply the proper Vgs voltage on the high side MOSFET , where the source is in fact the OUT of the power stage.

Referring the high side gate driver to the ground could cause gate-source breakdown of the MOSFET-

  • As I understand it high-impedance mode is used for communication bus so that it's in a undetermined logic state. However here we are driving motors, so what is the purpose of the high-impedance mode here?

ANS: In motor driving high impedance has the main purpose to impose no current into the windings.

9 replies

Enrico Poli
Enrico Poli
ST Employee
August 20, 2021

Hi @ARaj.1​ ,

The gate driver embedded in the STSPIN32F0 implements interlocking and does not allow to turn on both high side and low side MOSFETs of the same half-bridge at the same time (HSx = 1 and LSx = 1). In this case both high side and low side MOSFETs are turned off.

The HSx = 0 and LSx = 0 configuration is valid and properly managed by the gate driver turning off both high side and low side.

This is actually the default condition you have at the start-up.

If you need to force a single phase in high impedance, you should configure the TIM1 outputs connected to that phase accordingly.

You can use the six-step code example in the latest version of the Motor Control SDK (X-CUBE-MCSDK-Y) as guideline.

Kind Regards

Enrico

ARaj.1
ARaj.1Author
Associate II
August 20, 2021

I understand that HSx and LSx can't be 1 at the same time. The issue is I can't get them to be 0 simultaneously (I have confirmed this by measuring the voltage at the gate of the external high side and low side mosfets). Without setting up the timers, for example if I toggle PB13 (LS1) and PA8 (HS1) low as GPIO Outputs in the ODR, HS1 is always high and LS1 is low (at the output). The only way to drive them both low is to put the IC into standby mode i.e. OC_TH_STDBY1=0, OC_TH_STDBY1=0, which turns off all the phases and is not useful. My question is using just GPIO toggle how can we get both HS1 and LS1 low such that it is floating and the the current path is only through the other two phases.

Enrico Poli
Enrico Poli
ST Employee
August 20, 2021

Hi @ARaj.1​,

From the hardware point of view I can confirm you that the low-low condition is allowed, no circuitry should prevent this condition and it is used in our six-step firmware.

The gate driver die embeds pull-down forcing on all the driving inputs so even an high impedance status of the respective GPIOs should result in a low logic value.

Could you please share the code you used during your tests?

What about the voltages at the power stage output? Is the high side MOSFET on?

Terms & ConditionsAccessibility statement