STGIPL20K60 : Gate and control signals polarity and bootstrap sizing
Hi, i'm using a STGIPL20K60 IPM (SDIP-38L) .
I have a two questions :
- Regarding the control signals :
on ST website produt page regarding which states "Logical Function" : "Negative Input" ; this information is not stated in product's datasheet and not clear enough ?
And in the datasheet gate signals input (HIN and LIN = "NOT LIN") are mentioned, does this mean that wanted LIN signal have to be inverted ?
The truth table states quite the opposite and is contradictory with the waveforms (page 14). (maybe a typo?)
- Rearding bootstrap sizing :
the product's datasheet doesn't cite all the parameters for a correct (exact) bootstrap capacitor sizing (IGBT and driver parameters).
- VF: bootstrap diode forward voltage drop
- VRDS(on): DMOS voltage drop
and :
- QGATE: total MOSFET gate charge
- ILKGS: MOSFET gate source leakage current
- IQBO: bootstrap circuit quiescent
- ILK: bootstrap circuit leakage current
- ILKDiode: bootstrap diode leakage current
- QLS: charge required by the internal level shifters
I'll be glad if anybody could answer these questions or faced similar issues
