STGAP3SXI UVLO and RDY signal

[Mars_and_beyond]

Hello, I’m using 6 of the STGAP3SXI as part of an IGBT 3 phase bridge driver. Each chip has its own 24V to isolated +15V and -9V switching supply (Meanwell GD2-241509) and the logic side is powered with a separate +5V supply. Everything runs normal except once in a while I get a random low signal on one of the chips on the READY pin which causes the MPU to issue a fault and shutdown.

The datasheet says this is an error signal for the logic side under volt lockout, the isolated side under volt lockout, and the chip over temperature sensor. The diagram shows that the READY signal will return high after the voltages have risen above the min thresholds and chip temperature has lowered. However, the voltages from the supplies are above the UVLO thresholds on both sides and the chip temperature is nowhere close to its trip point. Also, when this occurs, the READY signal never returns high and only a total power down will reset it. 

Is this a noise issue locking up some function of the chip? I use all the recommended bypass caps and have tried several others but nothing I do seems to make a difference. Is there something I’m missing thats not in the datasheet? 

Could it be triggering the Watchdog and what does “condition is maintained until communication link is properly established” mean?

Thank You

[Richard Li]

Did you check softoff and Desat signal when “low signal on one of the chips on the READY pin”?

[Mars_and_beyond]

Yes, the desat pins are all normal, but I didnt check the softoff… thats a good point. It just looks like the RDY pin stays low and even pulling the chip RST pin low-high has no effect. But I’ll look at the softoff.

Thank You!