STGAP3SXI UVLO and RDY signal

[Mars_and_beyond]

Hello, I’m using 6 of the STGAP3SXI as part of an IGBT 3 phase bridge driver. Each chip has its own 24V to isolated +15V and -9V switching supply (Meanwell GD2-241509) and the logic side is powered with a separate +5V supply. Everything runs normal except once in a while I get a random low signal on one of the chips on the READY pin which causes the MPU to issue a fault and shutdown.

The datasheet says this is an error signal for the logic side under volt lockout, the isolated side under volt lockout, and the chip over temperature sensor. The diagram shows that the READY signal will return high after the voltages have risen above the min thresholds and chip temperature has lowered. However, the voltages from the supplies are above the UVLO thresholds on both sides and the chip temperature is nowhere close to its trip point. Also, when this occurs, the READY signal never returns high and only a total power down will reset it. 

Is this a noise issue locking up some function of the chip? I use all the recommended bypass caps and have tried several others but nothing I do seems to make a difference. Is there something I’m missing thats not in the datasheet? 

Could it be triggering the Watchdog and what does “condition is maintained until communication link is properly established” mean?

Thank You

[Richard Li]

Did you check softoff and Desat signal when “low signal on one of the chips on the READY pin”?

[Mars_and_beyond]

Yes, the desat pins are all normal, but I didnt check the softoff… thats a good point. It just looks like the RDY pin stays low and even pulling the chip RST pin low-high has no effect. But I’ll look at the softoff.

Thank You!

[Mars_and_beyond]

Checked that and that doesnt seem to be a problem. The softoff is activated anytime a fault is detected by the chip anyway. I tried toggling the RST pin but that has no effect. I also tried sending switching signals since I pull all to low on any fault.. again, no effect. According to the data sheet, that is only used to reset from a Desat fault which I never see. The chips RDY pin is suppose to automatically come out of a fault condition whenever the UVLO or the over temperature moves back into the allowed ranges, but the RDY pin always stays low until a complete power down and power up is done.

This to me seems to be some kind of a chip controller lockup. Maybe due to noise or whatever… I’ve been reducing the switching noise on the power supply pins and it seems to help at little. I’ll keep at it.

Thank You

 

[db16122]

 

For READY with UVLO protection, two kind for waveform may need to check accroding to the datasheet. One is VDD which already checked with no problem accroding to your feedback. Another seems with VH supply pin. There are about 3.5us delay about tVDD-RDY and 20us delay about tVH-RDY. Please refer to EVLSTGAP3SXI Data brief Half-bridge evaluation board for STGAP3SXI IGBT galvanically isolated gate driver with protection for schematics as well as datasheet for layout recommendation 

[Mars_and_beyond]

Thanks for the reply! I pretty much followed the data sheets recommendation on layout and based a lot of the circuit on the EVLSTGAP3SXI Eval board schematic. I’ve even doubled and tripled the the size of the bypass caps but that seems to make little difference. Heres what I’m seeing after the fault occurs…

Logic Side Vdd = 5.08V

 VH to GNDiso = 15.88V

VL to GNDiso = -9.60V

Chip Temperature is approx 78 to 80 deg F

Both input drive signals are 0V

The RST pin is pulled low for 10ms then pulled back up to 5V

Under these conditions, the datasheet shows that the RDY pin should return high. However, the RDY pin remains low and the only way to get to return to 5V is an OFF/ON power cycle. 

I have all of the RDY signals from the 6 chips in parallel to provide a single error line into the MCU. I’ve isolated this to individual chips but it seems to happen at random among all the chips.

Other than this problem, the driver chips work really well. Thank you for the insight and I’ll keep digging into it.

 

 

[Richard Li]

For big company product, before production, validation should be trusted, so this is a corner case , you should focus at special conditions.  

[Richard Li]

So this circuit into one Self-locking stage, you may not catch real condition, should be couple signal combination together cause this.

For me, debug can use two methods,

1. 1. try fig-out what’s happen,(If you have 4 channels scope)
2. a. catch diag, softoff,RDY, RST signal at fault time, 
3. b. Look for diag, softoff RDY, CLAMPdrv at fault time.
4. 2.  If 1 doesn’t work, try adjust softoff RC, Desat RC, RST RC value, 
5.      any impact should be clue, even change make it worse.

 

 

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