STEF01 - what is the equivalent circuit of the ENABLE/FAULT pin ?

[AFARI.1]

The ENABLE/FAULT pin delivers back a voltage that provides the part status (Table 6 of the DS).

It is said that OK = 5V; thermal fault = 1.4V; power protection = 0V.

As this pin must be directly connected to a 3.3V FPGA pin, I made some measurements with various loads to GND for simulating it (the max voltage that can be applied to that FPGA pin is 3.45V), and discovered that below some 10's of kOhm, that voltage is something like 0V, and that only from 50 kOhm and higher, it starts to "exist" (something like 1.0V at 47kOhm load).

Is there any model of that ENABLE/FAULT pin available, so that I can determine the correct schematic for connecting that (theoretic) 5V signal to the 3.3V FPGA pin ?

By-side question: for which load (to GND) is the feedback voltage specified ?

I have experienced that the simple high impedance load of a voltmeter is sufficient for deeply influencing that feedback voltage, which varies between 2.5V and 3.5V when the voltmeter is loading it...

Loading that pin with a 100kOhm resistor makes the voltage to drop to only 2.0V (instead of the nominal 5V voltage)

[Peter BENSCH]

Despite the fact the internal circuitry behind ENABLE/FAULT is currently not available, you might make use of some informations given in the datasheet. In table 5 it gives the Low level input current for that pin, which is internally driven by a current source. Its typical value of 20µA matches exactly to your observation while connecting there a 100k resistor to ground.

You might want to consider some additional circuitry to determine the status of this pin based on the three levels there: 0V, 1.4V, 5V. FPGAs tend to have some difficulty distinguishing analog values. ;)

In case you mean with "feedback voltage" the output voltage of that ENABLE/FAULT, then you need to distinguish between 1.4V and something higher, e.g. 2.4V. Due to the current source mentioned above the load calculates to about 120k...infinite, resulting in 2.4...5V.

When your question is answered, please close this topic by choosing Select as Best.

Good luck!

/Peter

[AFARI.1]

Thanks Peter !

This confirms my initial findings.

RE: using an FPGA for acquiring this kind of analog signal, one can use their input buffers as pretty efficient analog comparators !

BR Alain