LED1642GW: Does it matter if the Latch (LE) signal is shifted within one word?

[Elias Zimmermann]

Posted on November 13, 2017 at 14:42

Hello,

according to the datasheet of the LED1642 driver, the LE signal value is defined by the number of CLK rising edges when the LE is 1.

In the datasheet, the figures always show LE signals which are aligned to the first rising clock edge of a new data signal (SDI) (like it is shown in the attached figure).

Is this a requirement we need to meet when implementing a driver? Is it valid, when the LE signal is high for a specified number of clock rising edges in the middle of a data signal block (16 bit)?

best regards

[Elias Zimmermann]

Posted on November 21, 2017 at 17:25

Does it matter?

The pictures show 16 clk - high signals, while the LE signal is high for 5 times on each picture. Is this valid?

[Elias Zimmermann]

Posted on December 15, 2017 at 12:54

push

[Elias Zimmermann]

Posted on January 12, 2018 at 08:30

Do I have to move this topic to somewhere else?

[Tesla DeLorean]

Posted on January 12, 2018 at 14:40

These are primarily engineer-to-engineer forums, not a way to access ST's FAEs, so getting answers is somewhat reliant on other sharing similar interests or problems.

There is an online support request form, and this might yield some answers from their internal FAQ and support ticket system.

For engineering support contact your local sales office.