L6388E design support

[Mat Maher]

Posted on June 27, 2018 at 15:21

Hi all,

I'm in the process of bringing up a new design using the L6388E gate drivers. However, I've run into a stumbling block. Hopefully its something stupid in the design, but I'm at a loss: was wondering if anyone has any ideas? 

I'm applying constant voltage to the HIN pin, but getting nout out on the gate line. All the other voltages are reading good, however. Cext calculations for these FETS come out at 8.3nF: so that 100nF bootstrap should be gross overkill. Voltage readings appended to the schematic below.

Any ideas?

Mat 

[Mat Maher]

Posted on June 28, 2018 at 08:56

forum nobbled the original picture...

[fabbri.fabio]

A late reply but i could helpful to others.

HVG could not rise up for a simple reason:

HIN pin sensible to edges (while LIN is sensible to level) once VCC and VBO(VBOOT-OUT) are not in UVLO state (above UVLOthon).

In other words, it is first required first to supply VCC, turn on low side Q2 to charge the bootstrap capacitor C11 by rising LIN. Only once C11 is charged you can rise HVG by rising HIN. If you keep it static from the beginning HVG cannot rise up.

Moreover L6388 have interlocking, to protect most application topologies, you cannot rise LVG and HVG simultanously. If for any reason your application need that, you can use devices like L6385, L6386, L6395 which does not have interlocking and can fit this requirement.

Additional note: for C11 is enough a 20V ceramic capacitor. 100nF is ok (maybe better 220-330nF)

Fabio