I plan to use an STPMIC1 to power a STM32MP157A with DDR3L. The only PMIC in stock is the STPMIC1E. For this particular case, will we have to pre-program the STPMIC1E before on a JIG tester or can it initially power the MPU which then programs the PM

[JCond.1]

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[PatrickF]

Hi,

I apologize for hard time to find components.

Did your initial plan is to use STPMIC1A (BUCK3=VDD=3.3V) or STPMIC1B (BUCK3=VDD=1.8V) ?

Please look at STPMIC1 datasheet (Table: "Default NVM configuration vs part number") to see if differences between part numbers are avoiding your platform to boot.

Apart few other differences, main differences Vs STPMIC1A are for BUCK3 and BUCK4 default voltage (BUCK1 rank and VINOK_Rise value difference are minor)

Check that STM32MP15x supplies needed to boot (usually VDD, VDDCORE, VDD3V3_USBxx) but also on boot Flash supplies (usually VDD or BUCK4) are present and in allowed range for each components.

If the platform successfully boot to TF-A and there is no power sequence violation, there is even no need to change the STPMIC NVM as I assume on each boot the TF-A software could start required STPMIC1 regulators and change their voltages using I2C.

You could change STPMIC1 NVM with uBoot, but this mean a successful boot up to uBoot.

If no suitable boot option is found, it is possible to re-program the STMPIC1 NVM before soldering as you mention.

It is even doable to program on the target a soldered STPMIC1C (i.e. blank NVM device, no output supplies after power on), using I2C and externally supplied VIO and VIN.

Regards.

[JCond.1]

Our initial plan was to use to STPMIC1A. This is mainly because we are basing our design off the evaluation board STM32MP157A-EV1, which uses the STPMIC1A with DDR3L. Our main concern currently is that the DDR3L needs 1.35 V but Buck 1 is set to 1.1 V for all the pre-programmed STPMIC1 versions.

[PatrickF]

Hi,

In our reference design boards, we use Buck2 for DDR. Trying to stick to existing will reduce your work.

Anyway, in STPMIC1, Buck2 is never started by default (rank=0) as DDR supply is not need for first stage boot (TF-A). Buck2 is started by SW at right voltage before initialization of DDR and load the next partition (for FIP/uBoot).

So default STPMIC1 voltage does not matter if rank=0.

As far as I see, STPMIC1A should be the highest runner within STPMIC1 references. This high demand might explain (hopefully temporary) allocation issues. On my side, I have no visibility on this.

Depending on your mass production date (if any large production), might sound better to stick the design with STPMIC1A (if fitting your needs) and find a way to externally program NVM of an STPMIC1E (or other suffix) as STPMIC1A for prototyping and small production.

Regards.

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[JCond.1]

Could you help us acquire some samples of STMPICA for prototyping? I wasn't sure which of the many sales departments to contact.

[JCond.1]

We're also exploring a power scheme consisting of discrete regulators. We notice that AN5256 "STM32MP151, STM32MP153 and STM32MP157 discrete power

supply hardware integration" provides good detail for such an approach. If we go this route, we would use a DDR3L power solution chip to provide VTT_DDR, VDD_DDR, and VREF_DDR. VDDCORE would be provided from a dedicated buck. VDD,VDD_ANA, VDD_PLL, VDD_DSI and other related would be star connected to another 3.3 buck. Since we don't intend to use ADC/DAC nor USB, can we simply not provide power to these domains? Looking at the datasheet, table 10 and table 13, it seems power pins related to ADC/DAC or USB can be set to 0 volts.

[PatrickF]

I think this question is followed in https://community.st.com/s/question/0D73W000001N0mo