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[ausera uirwaij]

Thank you.

[Cristiana SCARAMEL]

Hello @ausera uirwaij​,

which driving topology are you using: full-bridge or single half-bridge?

Could you share your schematic?

The DC motor current have a strange shape, please share an oscilloscope waveforms showing the current and voltage phase.

[ausera uirwaij]

Hello

[Cristiana SCARAMEL]

Hi @ausera uirwaij so you are using a three-phase motor​, good to know.

In the 6Step_Lib.c:

• Voltage Mode: speed loop output is the duty cycle (on-time) of the phase. So an increase of the speed corresponds to an increase of the duty cycle of the PWM output. With this driving mode the output current peak may change along the step.
• Current Mode: speed loop output is the duty cycle of the current reference of the current limiter. With this driving mode the output current peak is maintained at a constant level, controlled by the current reference. The duty cycle of the output phase is not constant since the phase is turned off as soon as the load current threshold is reached.

With current mode, the current is limited thanks to an external comparator (whose inputs are the reference and the voltage across the sense resistor) that triggers the start of the decay time. So a firmware current loop is not needed since the speed loop is the one that controls the current by means of the current reference connected to the comparator.

For further support in the original question please share the above requested oscilloscope waveforms showing the current and voltage phase.