Can we remove VSS power from 8 daisy chained L6470s but keep them powered by 1 external 3.3VDC supply via the VDD pins (ref. section 1-3 of ST Micro note AN4241) w/o damaging the parts? Will the L6470's retain their parameters w/o VSS but with VDD on

[EMcCa.1]

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[uomo motore]

VSS is the GND reference for all communication between the MCU and the daisy chained L6470s. Without connecting VSS, SPI communication will not work properly between multiple devices. On the other hand, the device has an internal 3.3V voltage regulator. Each device can generate the 3.3V logic supply from the higher voltage VSA/VSB inputs used to drive the stepper motors. VDD pin connected to internal VREG (3.3V) or external 3.3V/5V decides the logic level for communications. So you can probably eliminate external 3.3V supply but would need to connect GND between all devices.

Hope this helps...

[EMcCa.1]

Thanks for the reply. By VSS I meant VSA & VSB (H bridge power, not GND, which is always connected between all L6470s). On our system H bridge power is temporarily removed by safety interlock but that will stop all the internal 3.3VDC regulators. So we need external 3.3VDC to keep the logic powered so we don't have to home again. I was wondering if the L6470's will retain all its parameters if VSA&VSB is removed with external 3.3VDC still present. Also, could this damage the part? Some parts exhibit substrate latch up if power supplies are brought up out of sequence.

[Cristiana SCARAMEL]

No, you cannot remove the motor power supply​ (VSA and VSB) keeping powered the logic supply (VREG).

First, VREG is connected to VS pins through the internal regulator. Removing VS and keep the VREG could damage the device.

Moreover, when the motor supply voltage is missing the device is resets (some internal pre-regulated voltage are generated starting from VS).

In this condition the registers values are reset to default and all protection functions are disabled.

[EMcCa.1]

Thanks for the info. We haven't made PCB's yet so design revision of board & software can be done w/o big trouble. But we wonder why the app note illustrates how to use external 3.3V VDD if there could be such trouble. Systems with multiple power supplies often don't reach nominal voltage simultaneously so external VDD could be a problem at start up or shutdown. So why even mention external VDD's in the app note?

[Cristiana SCARAMEL]

The Application Notes shows the alternative supply scenarios (more details in the other you post).

The solution with external 3.3 V power supply allows to avoid the internal linear power dissipation.

In your previous question, you are referring to a static conditions (remove VS with VREG applied), during power-up and power-down phase the device is protected through the UVLO thresholds.