This behavior usually points to a timing/clock configuration issue rather than a pure signal integrity problem.
Enabling Hardware Flow Control and reducing ClockDiv improves the SDMMC/SPI timing margin, which can make write operations more reliable especially if the card is sensitive to command/data timing skew.
Even if the waveform looks clean, SDIO/SDMMC write operations are much more timing-critical than reads, so small setup/hold violations or internal FIFO timing issues can cause exactly this kind of “read OK, write fails” behavior.
It’s also interesting that both F407 and H750 show the same dependency that suggests it’s more about the SD card + interface timing combo rather than a single MCU bug.
Worth double-checking:
SD clock frequency vs spec limit of the card
CMD/DAT line pull-ups
SD bus mode (1-bit vs 4-bit)
FIFO/flow control settings consistency
Good catch on the fact that adjusting ClockDiv fixes it — that’s a strong hint it’s timing margin related rather than hardware damage or wiring issues.