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sami_josi
Associate II
October 9, 2026
Question

NTAG5 (NTP53121G0JTZ) I2C SRAM Mirror Mode — Multi-Block Write NACKs After First Block

Hello

Using NTAG5 Link (NTP53121G0JTZ) in SRAM Mirror mode with an STM32G0B1RE I2C master at 100 kHz. WDT is disabled (WDT_EN=0, WDT_CONFIG=0xFFFF).

Problem: A single I2C multi-block write to SRAM (64 blocks, 256 B starting at 0x0000) NACKs after the tag accepts exactly one 4-byte block.

Questions:

  1. Are multi-block SRAM writes supported in SRAM Mirror mode, or only in SRAM Pass-Through mode (AN12364)?

  2. If supported in mirror mode, what configuration am I missing?

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