Technical Inquiry regarding L99DZ300G EI1 Wake-up Configuration with 50Hz PWM Input
Dear STMicroelectronics Support Team,
I am writing to request technical clarification regarding the wake-up configuration of the L99DZ300G's EI1 pin. We are currently debugging an issue related to sleep mode and false wake-ups in our system.
[Background]
An external controller inputs a 50Hz (20ms period) PWM signal to the EI1 pin for Crash Unlock detection. The signal operates as follows:
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Steady State: High 16ms (80%) / Low 4ms (20%)
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Crash State: High 4ms (20%) / Low 16ms (80%)
[Current S/W Configuration]
The EI1 pin is configured to Cyclic Mode using Timer 2:
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EI1_FILT[1:0]= 0x01 (Cyclic mode with Timer 2) -
Timer 2 Period = 20ms (T2)
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Timer ON Time = 0.1ms (ton1)
[Our Analysis & Concerns]
Based on the datasheet, our understanding is that the "blanking time 80% of timer ON time" applies to the 0.1ms ton (i.e., 80µs), followed by a brief 16µs sampling window ($t_{WU\_cyc}$).
Since the monitoring period (20ms) matches the input PWM period (20ms), we suspect an aliasing/phase lock issue. Due to MCU clock tolerances (phase drift), the 16µs sampling window could eventually fall into the 4ms Low duration during the Steady State. The datasheet mentions that an external interrupt is processed if the status has changed versus the previous cycle. Therefore, sampling the 4ms Low duration during the Steady State would trigger a false wake-up.
As a result, we concluded that the L99DZ300G cannot reliably distinguish between the 16ms and 4ms duty cycles using S/W configurations alone.
[Questions]
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Is our understanding of the cyclic monitoring mechanism (80% blanking of
tonfollowed by $t_{WU\_cyc}$ sampling) and its limitation in distinguishing PWM duty cycles correct? -
Is there any internal register configuration in the L99DZ300G that can reliably distinguish between the 80% and 20% duty cycle of a 50Hz PWM signal without causing false wake-ups?
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If S/W configuration is not feasible, would you agree that the best approaches are either adding an external RC Low-Pass filter to convert the PWM to a DC voltage, or requesting the upstream controller to halt the PWM output during Sleep mode?
We would highly appreciate your technical review and recommendations on this matter.
Best regards,
Jung-hoon Kim
Field Application Engineer
WTK
