SSPx frequency calculation error

[md1]

Posted on February 27, 2007 at 18:13

SSPx frequency calculation error

[gu48bz]

Posted on May 17, 2011 at 09:36

While on this general area I reported a bug while back which is pretty fundamental in the HAL. Never sure if my bug reports make it to the relevant people, so...

code snipit from 91x_ssp.c...

/* Configure the Mode */

if(SSP_InitStruct->SSP_Mode == SSP_Mode_Slave)

{

/* Set the slave mode */

SSPx->CR1 |= SSP_Mode_Slave;

/* Configure the Slave output */

if(SSP_InitStruct->SSP_SlaveOutput == SSP_SlaveOutput_Disable)

{

/* Slave output disabled */

SSPx->CR1 |= SSP_SlaveOutput_Disable;

}

else

{

/* Slave output enabled */

SSPx->CR1 &= SSP_SlaveOutput_Enable;

}

}

else

{

/* Set the master mode */

SSPx->CR1 &= SSP_Mode_Master;

/* Clear clock rate SCR[7:0] bits */

SSPx->CR0 &= SSP_ClockRate_Mask;

/* Set the serial clock rate */

SSPx->CR0 |= (SSP_InitStruct->SSP_ClockRate<

/* Clear clock prescaler CPSDVSR[7:0] bits */

SSPx->PR &= SSP_ClockPrescaler_Mask; // WRONG, applicable to slave mode as well

/* Set the serial clock prescaler */

SSPx->PR |= SSP_InitStruct->SSP_ClockPrescaler; // WRONG, applicable to slave mode as well

}

SSPx->PR only gets set up in master mode, but not in slave. The consequences on Rev D silicon are pretty harsh. random reboots, ARM core total lockups, total loss of JTAG comms, it's major league stuff.

Also as a side note, running at a PCLK of 96MHz just doesn't fly with the SSP peripheral, it's unstable. 48MHz is far more friendly.

[md1]

Posted on May 17, 2011 at 09:36

Hi,

I think there may be a slight error in rev1 of the reference manual.

In section 10.4.6 (page 238), the following is quoted:

Quote:

The serial bit rate is derived by dividing down the input clock PCLK. The clock is first divided by

an even prescale value CPSDVSR from 2 to 254, which is programmed in SSP_PR. The clock

is further divided by a value from 1 to 256, which is 1 + SCR, where SCR is the value

programmed in SSP_CR0.

The frequency of the output signal bit clock SCLK is defined below:

fSCLK=fPCLK / (CPSDVR + (1+SCR))

For example, if PCLK is 3.6864MHz, and CPSDVSR = 2, then SCLK has a frequency range

from 7.2kHz to 1.8432MHz.

However, I think the formula should read fSCLK=fPCLK / (CPSDVR x (1+SCR)) to obtain the frequency range specified?

Martin.