SSM/SSI missing from SSP_CR1?

[spigeon]

Posted on May 15, 2007 at 11:05

SSM/SSI missing from SSP_CR1?

[spigeon]

Posted on May 17, 2011 at 09:43

Come on, no one ?

I know I can use a GPIO pin instead of controlling NSS manually, but really, it's a waste of a pin.

There has to be an explanation...

:o

[ben2]

Posted on May 17, 2011 at 09:43

I have exactly the same problem. The datasheet states you can use the the device in slave mode without requiring the use of the NSS pin. However the only way I could get the device to work was by using the NSS pin.

Either the datasheet is wrong, or there is a bug in the hardware.

I believe that the SSM=1, SSI=0 is possibly a typo and that

SSM is actually the MS bit and SSI is the SOD bit, but I could be wrong

Ben

[spigeon]

Posted on May 17, 2011 at 09:43

Hello,

The STR91X reference manual, on page 236, states that NSS can be managed by software by programming bits SSM=1 and SSI=0 in the SSP_CR1 register.

However, the SSP_CR1 register does not contain these bits. In fact, SSM and SSI are not referenced at all in any other page of the reference manual.

I know the STR7 has those bits in SPISCR register... Is this an error in the manual? Can I control NSS manually at all?

Furthermore, UM0233 (IAR STR91x library) states on page 171 that the SSP_InitStructure contains a member called 'SSP_NSS', but in the 91x_ssp.h file, 'SSP_NSS' is missing from the structure...!

Any ideas?

Thanks!

:)

(FYI, I use SSP0 in SPI mode to connect to a M25P16 serial FLASH with CPHA=1. I need NSS to stay low during the reception of an entire 256-byte page, but it seems the SPI hardware pulls it high between every byte it clocks out).

[ This message was edited by: spigeon on 14-05-2007 16:38 ]