PSRAM Interfacing

[mmgbmm]

Posted on December 27, 2009 at 19:23

PSRAM Interfacing

[tomas23]

Posted on May 17, 2011 at 10:00

Looks to me like misconfiguration of SCU_EMI register (LFBGA/LQFP), kinda like WRh/WRl work like UB/LB.

Try to change (see the register description in RM).

[armmcu]

Posted on May 17, 2011 at 10:00

Hi mmgbmm

Strange behavior!!!!

Could you please confirm that the default state of both EMI_WRHn & EMI_WRLn just after Reset is high ?

Normally all EMI control signal are output high state after and during RESET.

Cheers.

[mmgbmm]

Posted on May 17, 2011 at 10:00

Hi,

I’m trying to interface STR911FAW44X6 to a PSRAM device (MT45W4MW16BCGB). Unfortunately we’re using the LQFP128 package, which means we have to use some extra logic to get the correct interface.

The problem I have at the moment is that EMI_WRHn and EMI_WRLn are pulled low during a read cycle! Is there a register I have to set to prevent this?

We’re using Asynchronous mode only. The decode logic is:

UBn = EMI_WRHn & EMI_RDn

LBn = EMI_WRLn & EMI_RDn

WEn = EMI_WRHn & EMI_WRLn

Any help would be appreciated.

Thanks,

MM