Interrupts trigger in uPSD

[jgil]

Posted on May 22, 2003 at 16:30

Interrupts trigger in uPSD

[joseph2399]

Posted on May 17, 2011 at 11:54

Hi,

According to Table 37, when IT0 bit is SET, INT0 is triggered at the falling-edge. When IT0 bit is CLEARED, INT0 is triggered at the low-level. IT1 control bit works the same way for INT1.

[jgil]

Posted on May 17, 2011 at 11:54

hi,

I need some more information regarding the interrupts triggering in the uPSD3200 .

I don't know if INT0 and INT1 are triggered by positive level/edge (refer to page 38 of the uPSD321x data sheet ) or they're triggered by negative level/triggered ( refer bit IT0 of the register TCON at the table37 of datasheet).

Thanks in advance for any comments.

Regards,

Jokin