exiting from power down

[rkistner]

Posted on April 17, 2006 at 07:52

exiting from power down

[rkistner]

Posted on April 06, 2006 at 07:46

Hi,

sometimes when I'm exiting the power down mode via P2.5, the ST10F276 does not use the external clock but it's basic frequeny (~1MHz), although there's no problem with the RPD delay(~13ms) or the crystal.

I do see the external clock when passing the 2.5V at RPD.

I'm using a 8MHz crystal and the P0H7..5 are set to ''110''

I guess the PLL determines wheather there is a stable external clock or not after the RPD delay, correct?

[ This message was edited by: RK on 06-04-2006 11:29 ]