clock on address lines

[simpson]

Posted on September 24, 2004 at 03:09

clock on address lines

[simpson]

Posted on May 17, 2011 at 12:02

I have noticed on my board and the dk300 development that the address lines (AD7-0) Have a the system clock divided by a factor of 4 or 8 continulsly running. Even when the address lines are exercised the clock runs over the top. The clock goes from 0 3.3v whereas the address goes from 0 to 5v . Is this meant to occur? It doesn't seem to interfer with the operation on the development board. But I am expericencing some abigus problems with my application boards.

Thanks,

[ This message was edited by: tracman on 08-09-2004 02:11 ]

[joseph2399]

Posted on May 17, 2011 at 12:02

This is a stacked die device with the MCU running at 3.3V (5V tolerant I/O) and the PSD (memory+PLD) at 5.0V. You will see 3.3V or 5V signals depending on which device is driving the bus. Also keep in mind that there is a prefetch and branch queue that may explain why you see activity on the bus that is different from what you are used to with a typical 8032 core.

[lwang]

Posted on May 17, 2011 at 12:02

AD7-0 is the multiplexed address/data bus. uPSD33xx Preliminary Datasheet (May 2004) Fig. 86 on page 206 and Fig. 87 on page 207 show the waveforms during external “fetch� and “write� cycles respectively. They show 0V, 3.3V and high-Z levels. However, the actual waveforms are different and show 0V, 3.3V, and 5V levels. I think they did something funny to make it “5V tolerant�.