Clock duty cycle requirements, DIV2

[ryanrsrsrs]

Posted on February 17, 2005 at 11:58

Clock duty cycle requirements, DIV2

[ryanrsrsrs]

Posted on February 15, 2005 at 01:53

The reference manual states that RCCU_CFR:Div2 is used to ensure a 50% duty cycle.

What, exactly, is the duty cycle requirement for PLL1_in (CSU_CKSEL=1, CK2_16=1)?

And for CLK3=CLK2 (CSU_CKSEL=0, CK2_16=1)?

[olivier239955_stm1_st]

Posted on February 17, 2005 at 11:58

For the use of PLL1. it is mandatory to use the DIV2 divider. Therefore for configuration CSU_CKSEL=1, CK2_16=1 the 50% duty cycle is guaranteed.

For the case of CSU_CKSEL=0, CK2_16=1, for a 16MHz external oscillator a duty cycle of 60%/40% or 40%/60% should be acceptable.