SSC Driver support LSM6DSV for QCS8550 board

[sagar7046]

Hello Team,

We are using Qulacomm board QCS8550 Aikri kit with LE r90 release for production, In that there is SSC driver support of LSM6DSV

 

Our setup includes two LSM6DSVTR IMU sensors, and we are attempting to read and write sensor data over SSC using an I2C interface. The I2C bus has been configured in the JSON configuration file for the LSM6DSVTR.

 

Use Case Requirements:

Configuring both IMU sensors using the SSC driver with an I2C-based interface Using interrupt pins for data-ready signaling

 

Specifically:

INT2 must support an external pulse:

 

Current Status:

In the current driver implementation located at:

source/adsp_proc/ssc_drivers/lsm6dsv

 

From the driver code analysis, we observed that data is currently being received using a FIFO-based mechanism.

Additionally, it appears that the default driver implementation supports only the INT1 interrupt, while there is no implementation observed for INT2.

 

Problem Statement:

Our requirement is to generate an INT2 pulse for every sensor data sample.

For example, if the configured sample rate is 10 Hz, we expect one INT2 pulse per sample.

 

Currently we are not receiving any interrupt on INT2 pin of LSM6DSV,

Can you please help us to how to produce the DRDY interrupt on INT2 pin for SSC driver implementation ?

 

Lets us know if you required any additional information.

Also I have seen all the document releated to LSM6DSV, also seen the community forum, but i havent got any help related to our requirement.

Can you please help us or guide how to proceed ?

[abhargva]

Hello Sagar,

Regarding INT2:

To enable routing of interrupt over INT2, you need to do two changes:

1. In sns_lsm6dsv_build_config.h, set “#define LSM6DSV_INT2_SUPPORT           1”. Default is 0.
2. In platform registry file, set the irq_num for int2 in the MSB. Lower half is reserved for INT1 and Upper 32bits are reserved for INT2. Here is the relevant code for your understanding how the value you change in registry will be used:

          irq_config->interrupt_num            = (phy_sensor_pf_cfg->dri_irq_num & 0xFFFF);
          irq2_config->interrupt_num = (phy_sensor_pf_cfg->dri_irq_num>>16);
 

Feel free to contact Qualcomm if you need help updating the registry file.

 

Regarding DRDY interrupt:

The driver needs to pass Qualcomm PVL and Android requirements and hence it supports FIFO instead of DRDY. All use-cases should be satisfied with the FIFO implementation. if client application sets the watermark(report period) as 1, then it functions like DRDY. So no change should be needed.

 

Regards

[sagar7046]

Hello ,

Thanks for the reply.

 

Regarding INT2:

We have implemented the same changes in our source code, with a few modifications:

• The flag you mentioned, LSM6DSV_INT2_SUPPORT, is not used in the SSC source code for the R90 build on QCS8550. Instead, the flag INT2_SUPPORT is used. We have enabled this flag in the file sns_lsm6dsv_build_config.h.

• Additionally, we have updated the registry to support INT2.

In our setup:

• INT1 is connected to GPIO_192
• INT2 is connected to GPIO_200

In the registry JSON file, there is a parameter for interrupt lines called dri_irq_num, which is defined as:

dri_irq_num = (200 << 16) | (192)
            = 13107392

Hope this much change is enough in registery file.

 

Regarding DRDY interrupt:

How to sets the watermark(report period) as 1 ?

[Felixtom]

Hi,

Based on the current SSC LSM6DSV driver implementation, it appears the driver is primarily designed around FIFO-based data acquisition and INT1 handling. We could not find any existing support for routing DRDY events to INT2 within the provided SSC driver.

Could Qualcomm confirm whether INT2-based DRDY generation is supported in the current LE R90 SSC driver? If not, are there any recommended modifications or configuration changes to enable one DRDY pulse on INT2 for every sample (e.g., at 10 Hz, one pulse per sample)?

Any guidance or reference implementation would be greatly appreciated.

Thanks.

[sagar7046]

We have confirmed this with Qualcomm.

They indicated that additional updates are required in the sensor driver implementation. Since the LSM6DSV SSC driver is vendor-provided (STM), they request us to please coordinate with the vendor team to verify if any driver modifications are needed to support INT2 DRDY functionality.

 

[sagar7046]

Is there any update ​@Felixtom  ​@abhargva 

Can I get the help on this requirement.