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MGolm.1
Associate II
April 19, 2020
Question

Problem with Noisy output of LIS3DH accelerometer

Hello Everyone. I'm trying to use LIS3DH as vibration sensor and convert the output of acceleration to RMS velocity in range of +-4G and bandwidth of 10to1000Hz. But i encountered an odd problem with the LIS3DH output. When i set High pass filter to the 12Hz cutt-off or any other frequencies, I got many serious noisy output in all three axises. I tried to use just one single axis in x but still there are noises. I have to say that i'm using LIS3DH in low power mode with ODR=5.3KHZ. I will appreciate if anyone can help me to exit this lock-down situation in my design. Thank you.

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6 replies

Eleon BORLINI
ST Employee
April 23, 2020

Hi @Community member​ , did you enabled the FDS filter of the CTRL_REG2 (21h) register? This enable you to select the filter acquisition path as reported in the AN3308, p.17.

0693W000000WL30QAG.png

Btw, Did you check if the filter is working for lower ODR frequencies?

Regards

MGolm.1
MGolm.1Author
Associate II
April 25, 2020

Hi Dear @Eleon BORLINI​ . Yes I enabled FDS and I tested the issue with almost all ODRs and i got same results. When i disable FDS i get very good and stable output but as i enable the FDS to get the filtered data in output, Data are very unstable with high chattering and no any reasonable manner. The problem is in High pass filter itself. I use 4MHz SPI for getting data directly not from FIFO. Do you have any idea to use FIFO for solving the problem?

MGolm.1
MGolm.1Author
Associate II
April 25, 2020

I tested the FIFO output and again the same result when turning on the HPF.

EEstr.1
Associate II
May 8, 2020

¡Hola! ¿Lograste resolver el problema y obtener buenos resultados?

MGolm.1
MGolm.1Author
Associate II
May 10, 2020

Hi. After translating what you said i should say no. No solution and even no response from the ST company.

Eleon BORLINI
ST Employee
May 11, 2020

Hi @Community member​ , can you please share me the register configuration you are using, especially for the HPM1 and HPM0 bits CTRL_REG2 (21h) register? I would like also you to check if you are you facing the issue in every configuration (HR, NM and LP), by setting HR=1 in register CTRL_REG4 (23h). Regards