On the LPS22HB SPI, what is the minimum high time for CS?

[JPhil.3]

I'm communicating via SPI with an LPS22HB using an FPGA. Is there a minimum time specification between SPI transactions? I'm currently setting CS high for 0.5 SPC cycles between transactions, but this doesn't seem to work.

[Eleon BORLINI]

Hi @JPhil.3​ ,

I would say you have to take into account at least 1 clock pulse, since the internal logic has to understand the line has changed the polarity.

It is not directly reported in the datasheet p.12, but I would try (at least) with this value.

-Eleon