LIS2DUXS12 Smart Power mode - any trade-offs?

[Sigridur Eggertsdottir]

Hi,
I'm measuring the power consumption of the LIS2DUXS12 for FSM, MLC, and the step counter with or without Smart Power mode (SMART_POWER_EN bit in CTRL1). The current reduction matches my expectations (e.g. ~13.3 µA down to ~8.2 µA with 1 FSM program running). AN5909 describes the mechanism as dynamically scaling the supply current of the embedded function hardware blocks between "operating level" and "lower non-operating level".

My question: Is there any trade-off to enabling Smart Power mode besides the current savings?

 

For example:

• Any added latency?
• Any impact on accuracy?
• Any recommended ODR for Smart Power?
• Any settling time when switching between operating and non-operating levels?

I couldn't find this addressed in the AN5909 or the datasheet, and I haven't found any existing thread relating to this. Any clarification would be appreciated.

Thanks!

[Federica Bossi]

Hi ​@Sigridur Eggertsdottir ,

Smart Power mode mainly provides current reduction for embedded functions. According to AN5909, there is no stated impact on accuracy or latency, and no specific ODR recommendation for Smart Power itself. The only configuration aspect to consider is the execution-time threshold/window mechanism: if the algorithm execution time exceeds the threshold, Smart Power remains at operating level to ensure correct completion. Therefore, the main requirement is to tune the duration threshold using the actual embedded-function execution time in the target use case.

[Sigridur Eggertsdottir]

Thanks for the clarification on the execution time threshold mechanism. I dug into AN5909 and the SMART_POWER_CTRL register description in the datasheet and have a few more questions:

1. AN5909 states "If in at least one data-ready window the duration of the execution of the algorithms is greater than the duration threshold, the feature is disabled [...]” and it also states “[...] and the comparison is not performed anymore". If I'm reading this correctly, does that mean that Smart Power is disabled all together as soon as the algorithm exceeds the duration threshold? And if so, is there any mechanism that re-enables it?
2. If multiple FSM programs are enabled simultaneously/MLC program with more than one decision tree, is the execution time of FSM engine/MLC core evaluated as a whole? Since SMART_POWER_EN in CTRL1 and SMART_POWER_CTRL are both single registers, I would assume that the evaluation is done to the engine/core as a whole. Can you confirm or is my assumption off?
3. Following from question#2: If one FSM program has a long execution time while the others are under the duration threshold, could that single program cause the whole engine to exceed the duration threshold and disable Smart Power?
4. Based on the register description for SMART_POWER_CTRL, if WIN = 0000 the comparison is performed at each data-ready window, while WIN = N the comparison is done on N number of consecutive windows and then a definitive decision on enabling/disabling Smart power is taken. What's the intended use case or benefit for setting a number of consecutive windows instead of just letting it evaluate every window?

Thanks!