I'm using the LIS3DH. Do I need to provide a 90 mS delay between configuration of CTRL_REG1 and reading the OUT registers or the FIFO to insure stable output ?

[JMatt]

I'm using the LIS3DH. The Application Note AN3308 specifies a 90 mS delay time between configuration and reading data in the suggested procedure for performing a self test, (p57 of DocID18198 Rev 3). The delay is, "... for stable output".  Once ODR is set or FIFO enabled, is a delay required to insure stable data? If so, how long of a delay is adequate? 90 mS eats up a lot of power while the LIS3DH is just sitting there. Would 5 mS or 0 mS be OK?

[Eleon BORLINI]

Hi @JMatt​ ,

This 90ms delay refer to the Self Test condition only, which is sensible to small variation since the actuation force applied to the sensor (simulating a definite input acceleration) is huge. 

It is not necessary to wait such delay for a standard acquisition (continuous or FIFO mode).

Of course, you'll need 1/ODR to get a valid data after internal digital conversion. Moreover, it is a general recommendation to discard the first sample coming just after the register configuration.

For a general overview on the power-on timings, I suggest you to check the datasheet p.16 and 17 (following tables):

If my reply answered your question, please click on Select as Best at the bottom of this post. This will help other users with the same issue to find the answer faster. 

-Eleon

[JMatt]

Thank you.