Skip to main content
P
Pratyusha
Visitor II
July 10, 2026
Question

Assistance Required with SPI Communication on NBP8FD4ST1 Pressure Sensor

  • July 10, 2026
  • 1 reply
  • 58 views

Hi,

I am using the NBP8FD4ST1 pressure sensor with the S32K146 microcontroller. The CS_B/WAKE-UP pin of the sensor is connected to a GPIO pin on the microcontroller.

The logic analyzer signal mapping is as follows:

  • D0 → SCLK
  • D1 → CS_B
  • D3 → READY
  • D5 → MISO
  • D7 → MOSI

During the communication sequence, when I pull the CS_B pin low to request SPI communication, the READY pin is asserted as expected. After READY goes high, I send the SPIOPS register read command (0x00E1). However, the sensor always returns 0x0000 on MISO. As a result, the firmware validation fails, and the CS_B pin is subsequently driven high to terminate the transaction.

Could you please help me understand whether my SPI communication sequence is correct or if I am missing any required step, such as the wake-up sequence, dummy transfer, or SPIOPS handling described in the datasheet?

I have also attached the logic analyzer screenshots for reference.

Thank you in advance for your support.

Best regards,
Pratyusha.
 

 

1 reply

C
CamilleSJ
ST Employee
July 19, 2026

 Hi Pratyusha,

Thank you for the question and the details.

Let me start by saying that lowering the CS_B pin and waiting for READY pin to be asserted before starting the SPI transfers is correct. Now, from the screenshot that you shared, it looks like the CS_B and SCLK signals are not correctly driven by the Host during the SPI transfers.

Per SPI protocol, the Host (S32K in your case) needs to provide the clock (SCLK) and lower the chip select (CS_B) at every SPI transaction, which is 16-bit long for the NBP8. In your logic analyzer screenshot, I do not see any SCLK or CS_B activity while the MOSI command is being transmitted.

Below figure shows an example of CS_B and SCLK signals during SPI communication. These signals need to be driven by the Host. This figure is extracted from the NBP application note available at following link: https://www.nxp.com/docs/en/application-note/AN13882.pdf

 

 

For more details on the expected content of SPI transfers (including dummy read etc...), you can also refer to the sw user guide available in the doc folder of the example Host project at the following link: https://www.nxp.com/webapp/Download?colCode=NBP8x_Application&appType=license

 

The NBP-related resources are for now still on NXP website, but they will be migrated to ST website soon.

Hoping this will help,

Camille 

Terms & ConditionsAccessibility statement