STUSB4500QTR: does powering VSYS disable VBUS monitoring?

[wezdenkollc]

Hi,

 

I'm designing the STUSB4500QTR into a board that can run from USB-C, PoE or a DC jack. VDD is on VBUS as usual, and I'd like to run VSYS (pin 22) from our 3.3 V supply instead of grounding it, so the part can't hold the shared I2C bus low when the board is powered from PoE or the jack and USB-C isn't plugged in.

 

DS12499 Rev 8 seems to say two different things:

- Section 6.1.1 (p. 23): "there is an interest in using VDD pin only to supply the STUSB4500. First of all, this is mandatory to enable VBUS input voltage monitoring."

- Table 22 (p. 29): the VTHUSB (VBUS disconnection threshold) and VTH0V (vSafe0V threshold) rows give the condition "VSYS = 3.0 to 5.5 V". The table header says "Unless otherwise specified: VDD = 5 V, TA = 25 °C", so I can't tell whether those rows were measured with VSYS only, or with VDD and VSYS both present.

 

My questions:

1. With VDD on VBUS and VSYS at 3.3 V both present, does the STUSB4500 still monitor VBUS (VBUS_VS_DISCH, detach detection, and discharge at detach)?

2. If VSYS's supply is off while VDD is present, does any current flow from VDD into the VSYS pin or the 3.3 V rail?

3. Page 6 says SCL and SDA are pulled down "when none of VDD or VSYS is present". What is the impedance of that pull-down?

 

The application schematics in Figures 9 and 10 look like they ground VSYS, so I'd like to confirm before committing the layout.

 

Thanks,

Chris

[Peter BENSCH]

Welcome ​@wezdenkollc, to the community!

Yes, the datasheet supports VSYS = 3.3V while VDD is fed from VBUS. VBUS monitoring is still active in that case, and the monitoring thresholds in table 22 are explicitly specified for VSYS = 3.0...5.5V.

For your other points:

• The datasheet does not specify any reverse-current value from VDD into VSYS, so I would not assume “zero current” without board-level validation. If you really want to prevent the 3.3V rail from being affected via the IC, decoupling it through a switch/diode/power-path element is the more robust solution than simply switching it off directly without considering leakage paths.
• The SCL/SDA pull-down strength is not given as a resistance/impedance value; the datasheet only states that they are pulled down when neither VDD nor VSYS is present.

So, from the datasheet perspective, your proposed connection is plausible, but I would still validate leakage and bus behaviour on the real design.

Does that answer your questions?

Regards
/Peter

[wezdenkollc]

Thanks Peter, that answers it. Good to know VBUS monitoring stays active with VSYS at 3.3 V. That's the setup we have drawn, and it matches the STEVAL-ISC005V1 schematic.

Understood on the other two. We'll measure any leakage from VDD into the 3.3 V rail and check the I2C bus behavior on the prototype, and isolate VSYS with a diode or switch if it turns out to matter.

Thanks again,
Chris