Question
SR5E1 PRAM_AXI do not support Exclusive Monitor (ldrex/strex)
Even though in the documentation there is an explicit paragraph declaring that “Exclusive monitor” are present (I cannot copy here, the documentation states that I’m not allowed), but my test seems to prove otherwise.
If I try to use ldrex/strex on a variable i SRAM (MPU RASR configured for Shareable, Non-Cacheable, Non-Buffereable) I get a BusError, if I remove the Shareable bit the the exclusive mechanism do not work.
Could someone confirm my analysis?
Regards