SPC58NH92E7: VDD_HV_IO_MAIN never reaches 3.3V under load — board-level causes eliminated, need input

[Vincent0909]

Hi all, hoping some of the veterans here or an ST engineer can help. Long debug session, board-level causes systematically ruled out, looking for input on what's left.

Setup: SPC58NH92E7RMI0X (eLQFP176), custom board, internal-regulator-with-external-ballast configuration (BC868ballast transistor).

Core symptom: VDD_HV_IO_MAIN, fed from a confirmed-clean 3.3V LDO, never reaches 3.3V once connected to the MCU — plateaus around 1.3–1.8V regardless of available current (tested to 800mA–1A limit, current settles 500mA–1.5A depending on config). VDD_LV never stabilizes at 1.2V as a direct consequence. MCU runs very hot; the ballast transistor does not.

Ruled out:

• Wrong part (physically confirmed)
• Wrong pinout: every power/config/Ethernet pin checked against the official IO definition workbook
• Passive short on VDD_HV_IO_MAIN (~2.9kΩ unpowered, not a short, higher than an unrelated rail on the same board measured the same way)
• Wrong component values/orientation on the ballast circuit
• A real power-sequencing violation between VDD_HV_IO_MAIN and VDD_HV_ADR_S/ADV_S (found via scope, fixed, no change to core fault)

Reproduces identically on 2 boards, including an isolated bench test feeding only the MCU's 3.3V rail directly.

Questions:

1. ST's own SPC58NHADPT176S reference design (UM2731) uses an NJD2873T4G (D-PAK, 2-3W) ballast transistor vs. our BC868 (SOT89), is the smaller part adequate?
2. That reference design ties the ballast collector to VDD_HV_IO_MAIN. We tested that exact topology, VDD_LV got worse, not better. Does that point to the fault being upstream, in VDD_HV_IO_MAIN itself?

Attaching oscilloscope captures and the relevant schematic section. Any input appreciated