How to enable and disable JTAG on SPC58NN?
Dear community,
I have reviewed the following sections in the reference manual:
86.5.1 Censorship
86.5.2 Debug Interface Access
These sections describe the mechanisms for disabling the debug port.
After organizing and analyzing the relevant content, my current understanding is as follows: We first generate a hex file to configure the device lifecycle to the In-Field stage. In this state, the debug port will be disabled when the Lock3[DBL] bit is in the locked state.
However, I have noticed the following warning in the documentation.
Could you please provide the standard operating procedures (SOPs) for both enabling and disabling the debug port?
It would be greatly appreciated if reference code or timing diagrams could be attached.
Thank you in advance for your support.
Best regards