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TCabr.1
TCabr.1
Associate
May 2, 2022
Question

Wich is the STM32F429 PLLN maximum frequency?

  • May 2, 2022
  • 3 replies
  • 5870 views

User' manual says that the maximum PLLN or VCO output frequency should be between 100 and 432 MHz (pg. 227). However, I was trying to set the PLL clock and the SysClock to 180 MHz and also respect the 48 MHz clocks.

One possible solution is to set the PLLM to 4, PLLN to 360, PLLP to 4, and PLLQ to 15. Although, it leads to a VCO output frequency of 720 MHz.

The curiosity was that it worked. USB frequency is at 48 MHz, PLL and SysClock are at 180 MHz. So, my questions are:

1 - What are the problems with the VCO output frequency at 720MHz?

2 - I'm using USB HS, not the FS one. So, should I keep the USB FS clock at 48MHz?

3 - How should I configure PLL to operate at 180 MHz and use the USB HS?

Ps. My PLL clock source is HSE at 8MHz.

This topic has been closed for replies.

3 replies

TDK
TDK
May 2, 2022

1) The max VCO_OUT frequency is 432 MHz per the datasheet. If you go beyond that, maybe it works, maybe not, but it's not guaranteed. Maybe it works at most conditions but will fail at temperature extremes.

2) If you're using USB HS with the internal FS PHY, you need a 48 MHz clock. If you're in HS mode with an external PHY, you don't need this clock (but the external PHY chip will allow you to supply one to it).

3) If you need the 48 MHz clock, you can't. 168 MHz is the best you can do.

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TCabr.1
TCabr.1Author
Associate
May 3, 2022

After a lot of discussions, readings and tests, we come to the following @TDK​ :

1 - We need a manifestation from ST regarding if we can work at 720 MHz (VCO clock) once our power source always will deliver 3.3V. So, I flagged this post.

2 - Yes, you're right. We're using internal PHY, so the 48 MHz is necessary.

3 - Looking forward to ST's response.

Thanks again.

A
Alexander Czajor
Community Manager
May 4, 2022

Hello @TCabr.1​ 

The obvious standpoint is the one of @TDK and @Community member​. Using the chip outside the specification is risky and will sometimes work, sometimes not. There might even arise quality issues, as using the VCO outside the spec can cause additional stress to the device with respect to ST's testing conditions.

If you need further assistance with this point I would recommend to use the online support channel in the support channel.

Many thanks

Alexander

TCabr.1
TCabr.1Author
Associate
May 2, 2022

First of all, Tanks for your answer.

Secondly, I understand that use should respect what is on the datasheet and the user's manual. But, when I go to the device datasheet, pg 124 - table 43 - Main PLL characteristics, It says that the characteristics are "derived from tests performed under temperature and VDD supply voltage conditions summarized in Table 17".

When I go to Table 17, I notice that Vdd ranges from 1.7 to 3.6V.

Once my application always operates at 3.6V, and as the VCO is a voltage-controlled resonator, I ask myself, "Could I have a VCO_OUT at 720 MHz?"

Tesla DeLorean
Tesla DeLorean
Guru
May 2, 2022

Well I've certainly worked with courser geometry chips which wouldn't have issues with 600-800 MHz VCO frequencies.

Likely to pull more power in the VCO and divider chains. Seem to recall the F2/F4 wanting something like 2 - 4 MHz for the PLL comparison frequency.

You'd get to test, characterize and qualify what you're comfortable shipping

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Piranha
Piranha
Principal III
May 2, 2022

There is another way how to look at this. Decreasing the CPU clock from 180 MHz to 168 MHz, you are losing less than 7% of the clock cycles. If such a loss is critical, then the project is doomed anyway. If it's not critical, you can afford losing those few %.

TCabr.1
TCabr.1Author
Associate
May 2, 2022

Well, I sure can look this way. But, I'm trying to gain some %. In fact, increasing my PLL frequency by 7% leads to an application improvement of about 32%.

Piranha
Piranha
Principal III
May 2, 2022

That's interesting. What is it doing (from a technical standpoint)? Also an "impolite" question - is it using CubeMX/HAL code?

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