STM32L1xx: why CubeMX alerts me APB1 frequency should be >= 10MHz ?

[Cesare Riva]

Posted on May 30, 2018 at 12:18

Good morning to everyone,

I am developing a low power application on STM32L151RET6, the clock is generated by MSI @4.194 MHz. In this configuration I am experiencing some strange behaviour when I use the ADC synched by Timer4, in fact the resulting sample frequency seems not correct and if I change the source clock from MSI to HSE+PLL @6MHz the ADC even doesn't start (no ADC callback is invoked).

If I configure the clock configuration using CubeMX (latest version 4.25.1) surprisingly it warns me that APB1 clock must be >= 10MHz.

If I look at the STM32L151RET datasheet, table 13, paragraph 6.3.1 (page 61, rev.9) the section 'General operating conditions' reports that the min and max values of APB1 clock frequency should be from 0 to 32Mhz.

So, is there a real limitation on minimum APB1 clock frequency? I read again the STM32L1X Reference Manual but nothing I could find out more.

Thank you in advance.

[Artur IWANICKI]

Posted on May 30, 2018 at 13:37

Hello,

I was not able to reproduce your issue. But there is one thing I would correct in your clock settings ->  /PLLDiv should be 3 or 4 instead of to not exceed HCLK max in case you would switch to PLLCLK again.

Could you please pass me your STM32CubeMX .ioc project?

Thank you in advance,

Best Regards,

Artur

[Cesare Riva · Accepted solution]

Posted on May 30, 2018 at 14:31

Thank you for your reply Arthur,

the ADC was not working because I forgot to switch on the HSI oscillator.

Anyway, I found out why CubeMX was warning me about APB1 >= 10 MHz. The warning comes out only if the USB device is enabled.

Disabling the USB device I don't get that warning anymore.

[Tesla DeLorean]

Posted on May 30, 2018 at 14:41

The big hazard here is really what's defined as 'clock inversion', when you have multiple clock domains you have to special case synchronization where you migrate into a faster domain. Most of the bus hardware here expects to enter another sub-domain with the same or lower clock speed.

USB has issues, SDIO/SDMMC has issues. Some peripherals also take multiple clocks, and expect a PLL to be running. In some parts I2C has specific frequency expectations as a starting point. In some cases FIFO's are used to provide elasticity between buses with different speeds or cycle deadlines.

[Cesare Riva]

Posted on May 30, 2018 at 14:55

Very clear explanation.

Thank you.