The STM32MP157 has a maximum of 2 DSI data lanes. Is it feasible to run a 1280x800 display with only 2 lanes?

[Rc.1]

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[Tesla DeLorean]

They say 1Gbps per lane so probably, 1280x800x60x24 is about 1.5Gbps 1280x800x50x24 about 1.2GBps, plus some margin for line totals. The pixel clock ceiling is 90 MHz, so well below that.

The STM32 MCU's it's 500 Mbps per lane (1Gbps total). I thought the MP1 was about 1.5GBps total originally, but that seems to have changed. The specs do call out 1920x1080x30x24 as viable, and that's out at around 1.5 GBps.

https://www.st.com/content/st_com/en/products/microcontrollers-microprocessors/stm32-arm-cortex-mpus/stm32mp1-series/stm32mp157/stm32mp157f.html

[PatrickF]

@Community member​ answer is right, in STM32MP157 datasheet you will see "up to WXGA (1366 × 768) @60 fps or up to Full HD (1920 × 1080) @30 fps"

Both are about 1.5Gbits/s and so your use case with 1280*600 @60fps will be ok on 2 lanes (assuming the display is supporting it, 1Gbits/lane is not so frequent, this explain why most are 4 data lanes).

By my experience, I usually use a x 1.4 factor to take into account all 'non-pixel' times (protocol overhead, porchs, sync etc...) including enough margins.

Here 1280x800x24x60 x1.4 is 2.06Gbits, which is ok as the x1.4 factor is conservative and your pixel rate is even slightly below the 1366*768 @60fps we have tested.

Regards.