Why SRAM address is not changing after writing in it using STM32F429

[jagdish2]

Hi,

Having our board in which we have interfaced STM32F429 to SRAM (IS61WV204816BLL) .

Facing issue while reading back the data after writing.

Actual scenario:

Have written a SRAM test code in which am writing 10 bytes starting from SRAM location 0x64000000, using int write buffer of array size 10.

When am reading back the data from all 10 locations in read buffer of similar size, i found that, all 10 locations of read buffer is filled with 10th location data.

here is the init sram fn details

/*======================*/

/* FMC Configuration ---------------------------------------------------------*/

 /* SRAM Timing configuration */

 NORSRAMTimingStructure.FMC_AddressSetupTime = 2;

 NORSRAMTimingStructure.FMC_AddressHoldTime = 1;

 NORSRAMTimingStructure.FMC_DataSetupTime = 2;

 NORSRAMTimingStructure.FMC_BusTurnAroundDuration = 1;

 NORSRAMTimingStructure.FMC_CLKDivision = 1;

 NORSRAMTimingStructure.FMC_DataLatency = 0;

 NORSRAMTimingStructure.FMC_AccessMode = FMC_AccessMode_A; 

 /* FMC SRAM control configuration */

 FMC_NORSRAMInitStructure.FMC_Bank = FMC_Bank1_NORSRAM2;

 FMC_NORSRAMInitStructure.FMC_DataAddressMux = FMC_DataAddressMux_Disable;

 FMC_NORSRAMInitStructure.FMC_MemoryType = FMC_MemoryType_SRAM;

 FMC_NORSRAMInitStructure.FMC_MemoryDataWidth = SRAM_MEMORY_WIDTH;

 FMC_NORSRAMInitStructure.FMC_BurstAccessMode = SRAM_BURSTACCESS; 

 FMC_NORSRAMInitStructure.FMC_AsynchronousWait = FMC_AsynchronousWait_Disable;  

 FMC_NORSRAMInitStructure.FMC_WaitSignalPolarity = FMC_WaitSignalPolarity_Low;

 FMC_NORSRAMInitStructure.FMC_WrapMode = FMC_WrapMode_Disable;

 FMC_NORSRAMInitStructure.FMC_WaitSignalActive = FMC_WaitSignalActive_BeforeWaitState;

 FMC_NORSRAMInitStructure.FMC_WriteOperation = FMC_WriteOperation_Enable;

 FMC_NORSRAMInitStructure.FMC_WaitSignal = FMC_WaitSignal_Disable;

 FMC_NORSRAMInitStructure.FMC_ExtendedMode = FMC_ExtendedMode_Disable;

 FMC_NORSRAMInitStructure.FMC_WriteBurst = SRAM_WRITEBURST;

 FMC_NORSRAMInitStructure.FMC_ContinousClock = CONTINUOUSCLOCK_FEATURE;

 FMC_NORSRAMInitStructure.FMC_ReadWriteTimingStruct = &NORSRAMTimingStructure;

 FMC_NORSRAMInitStructure.FMC_WriteTimingStruct = &NORSRAMTimingStructure;

 /* SRAM configuration */

 FMC_NORSRAMInit(&FMC_NORSRAMInitStructure); 

 /* Enable FMC Bank1_SRAM2 Bank */

 FMC_NORSRAMCmd(FMC_Bank1_NORSRAM2, ENABLE);

/*======================*/

kindly guide to resolve the problem.

best regards,

Jagdish

[waclawek.jan]

Observe signals on the SRAM using logic analyzer, it should indicate what happens.

JW

[Tesla DeLorean]

Suggests it is not functioning.

Perhaps review code and performance of STM32429I-EVAL board, a working and proven design.

https://www.st.com/en/evaluation-tools/stm32429i-eval.html

Check all pin configurations and clocks.

Use a scope and logic analyzer to validate the design, and signals presented at the device interfaces.

The HW and SW design engineers need to do their due diligence of the design from schematic to board as fabricated, and do board bring up and validation.

[jagdish2]

Thanks for the inputs. Shall revert after validating the hardware design and firmware.

Jagdish

[jagdish2]

Hi, Found mismatch. The reference schematic used for developing our board was of STM32F7X6G-Eval board and HAL layer which i was using was of STM32F4.

Corrected the pin requirement, Bank No, etc.

Now the problem is resolved. and i am able to write and read from SRAM accurately

Thanks to everyone for their time and valuable advice.:)