Why does the STM32H743 reference manual talk about Cortex-M4 on the SRAM pages?

[Nikita91]

In the RM0433 rev 7 in the Embedded SRAM chapter:

AHB SRAM1 is mapped at address 0x3000 0000 and accessible by all system masters except BDMA through D2 domain AHB matrix. AHB SRAM1 can be used as DMA buffers to store peripheral input/output data in D2 domain, or as code location for Cortex®-M4 CPU (application code available when D1 is powered off. 

Does this mean that the M7 cannot put code into it? But there is no M4 in this MCU.

[TDK]

Surely it's just an error from copy/pasting the RM0399 section from the H745 manual, which does have the M4 core but is otherwise the same.

[Uwe Bonnes]

H743 latest revision and H745 are the same chip, with functionality disabled for the H743

[Imen GH]

Hello,

I take your feedback into consideration.

I will raise internally to correct

Thank you,

Regards

[berendi]

Theoretically the M7 core could execute code from AHB SRAM, but it would make little sense, as the M7 can access the AXI SRAM a lot faster.

[Nikita91]

I think so. It's better to put RAM code in ITCM which is made for that.

I was just wondering if the curious wording of the manual was hiding something I didn't understand.

Thank you.